Research window: Past 24 hours (2026-09-09 08:18 ~ 2026-09-10 08:18, Beijing time) Sources: Hacker News, CNX Software, ServeTheHome, Electropages, Electronics World, New Electronics, Google News aggregation (unreachable in this window; replaced by Tavily search), IICIE official agenda page, vendor official sites, GitHub API (org repo pushed and commit search, direct connection), etc. (see appendix source verification table for details)

Collection anomaly note: External retrieval channels (Google News RSS and GitHub-related channels) remained unreachable during this window; this issue instead uses direct GitHub API and Tavily search as substitutes. See appendix and the limitations note at the end.

Issue Index

  • I. Open Source Community and Software Ecosystem
    • XiangShan: Structural refactoring of the vector execution pipeline (removal of the VFAlu/VFMA wrapper layer), Dashboard releases 1.0.0 and adds Zicfilp template (09-09)
  • II. Product and Ecosystem Updates
    • Waveshare launches ESP32-C5 Pico board: dual-band Wi-Fi 6 RISC-V micro board in Raspberry Pi Pico form factor (09-09)
    • GigaDevice podcast discusses RISC-V, robotics, and edge AI: GD32 dual-architecture roadmap and EtherCAT distributed control (09-09)
  • III. Domestic Team Updates and Deep Dives
    • SpacemiT: Next-generation coherent interconnect bus N200 development completed, forming three major segments of general computing + intelligent computing + interconnect (released 09-07, added in this issue)
    • Nuclei: UK media reviews Quintauris RISC-V ecosystem collaboration, Nuclei automotive-grade IP aligns with RT-Europa (English media review 09-08~09, collaboration itself from H1 2026)
    • Comprehensive window observations: DAMO XuanTie Hypervisor Za* tests merged into statistics scripts, Sophgo SG2044 UEFI, Sipeed NanoKVM routine iterations (09-09)
  • IV. Embodied Intelligence and Robotics Special Chapter
    • Shenzhen IICIE Day 1: RISC-V Industry Ecosystem Innovation Conference agenda and exhibitor lineup confirmed, on-site coverage pending (09-09)
  • V. Summary and Trend Observations
  • Appendix: Source Verification Table and Complete Source List

I. Open-Source Community and Software Ecosystem

1.1 XiangShan: Structural Refactor of Vector Execution Path (Removal of VFAlu/VFMA Wrapper Layers), Dashboard Releases 1.0.0 and Adds Zicfilp Template (09-09)

Date: 2026-09-09 (Beijing time batch from 09:26 that day to 06:45 the next day)　Source: GitHub openxiangshan/XiangShan commits, XiangShan-Dashboard, difftest, XiangShanLab

The vector subsystem of the XiangShan open-source high-performance core (Kunminghu) has shifted from “feature rollout” to “structural refactor”: at 22:06 on 09-09, two adjacent commits respectively removed the VFAlu and VFMA wrapper layers for vector floating-point operations (refactor(vector): remove VFAlu wrapper and set fuGen to null in VfaluCfg, remove VFMA wrapper and set fuGen to null in VfmaCfg), switching to direct generation via functional unit configuration. This is a path cleanup following the consecutive merges from 09-06 to 09-08 (whole-register move, vfma/vfmac and widen instructions, VIDiv vector integer division), and typically indicates that this group of instructions has entered stabilization and a preliminary stage for subsequent matrix/reduction operation extensions. Other commits in the same window cover frontend and execution details: 09-09 23:36 fix(decode,rename): handle JAL/JALR link and jump uops (author date 05-08, a wrap-up merge of a long-running branch batch), 09-09 09:26 fix(I2F): pipeline move op's fflags result signal (#6519), 09-09 15:17 ci(emu): determine emu-mc threads with verilator version (#6517). On the supporting side: XiangShan-Dashboard released release: 1.0.0 at 03:10 on 09-10 and added version and build-time badges; difftest merged fix(fpga): recover specified name of XMR probe (#959); XiangShanLab added a Zicfilp (landing pad jump target validation extension) template; GEM5 added a repository code owner. Within the window, 16 repositories in the openxiangshan organization (XiangShan, difftest, GEM5, CoupledL2, XSCache, gsim, rocket-chip, ZhuJiang, etc.) had pushes, remaining the most active open-source core team at present, with verification and toolchain support evolving in sync.

II. Product and Ecosystem Updates

2.1 Waveshare Launches ESP32-C5 Pico Board: Dual-Band Wi-Fi 6 RISC-V Micro Board in Raspberry Pi Pico Form Factor (09-09)

Date: 2026-09-09　Source: CNX Software, Open Source For You, Waveshare Documentation Site, GitHub waveshareteam/ESP32-C5-Pico

Waveshare has released the ESP32-C5 Pico board, bringing Espressif’s ESP32-C5 dual-band Wi-Fi 6 SoC into the Raspberry Pi Pico form factor (approximately 51 to 56.85 x 21 mm). Key specifications: ESP32-C5-MINI-1/1U module (ESP32-C5HF4, single-core 32-bit RISC-V up to 240 MHz plus a 48 MHz low-power RISC-V core, 384 KB SRAM, 320 KB ROM, 4 MB SPI flash); wireless support for dual-band 2.4/5 GHz 802.11ax Wi-Fi 6 with Wi-Fi 4 backward compatibility, Bluetooth 5.0 LE (including Mesh), and 802.15.4 (Zigbee 3.0 / Thread 1.3 / Matter). On-board USB-C (power, flashing, charging), 2x20 pin Pico-compatible headers (up to 26 GPIOs, 20 PWM channels, plus 6 more via TCA9554PWR expander), reset and BOOT buttons, RGB LED, and lithium battery charge/discharge circuitry; available in four versions (on-board PCB antenna or IPEX external antenna, headers pre-soldered or unsoldered), with software support for Arduino IDE and ESP-IDF, and example code migrated from the official website to GitHub (board info, RGB, I/O expansion, dual-band Wi-Fi, UART, 1.83-inch touchscreen, MCP2515 SPI CAN, etc.). Significance: Since the ESP32-C5 entered mass production in April 2025, its “dual-band Wi-Fi 6 + RISC-V” capabilities are spreading downmarket along the Pico-compatible form factor, with the third-party board ecosystem (Waveshare being a Shenzhen manufacturer) serving as a direct amplifier for Espressif’s RISC-V wireless MCU deployment.

2.2 GigaDevice Podcast Discusses RISC-V, Robotics, and Edge AI: GD32 Dual-Architecture Strategy and EtherCAT Distributed Control (09-09)

Date: 2026-09-09　Source: Electropages, GigaDevice Humanoid Robot Solution Page, GigaDevice GD32V Launch Announcement

In an Electropages podcast (Robin Mitchell in conversation with GigaDevice Business Development Manager Kevin Jones), the company’s MCU strategy was discussed systematically: on RISC-V, GigaDevice was an early mainstream adopter, launching the GD32VF103 back in 2019 (with the core provided by Nuclei, a publicly acknowledged collaboration), and its current wireless product line also uses RISC-V; the company emphasizes that architectural flexibility allows chip vendors to customize processors around specific applications and workloads. On robotics, the multi-motor and complex motion requirements of industrial robots are raising determinism demands for inter-controller communication; the GD32H7 series supports EtherCAT, enabling distributed MCUs to each control individual motors and local subsystems, reducing reliance on sending all decisions back to a central processor. On edge AI, local inference tasks such as motor anomaly detection and human presence detection need not depend on high-end AI processors; Cortex-M7/M33 can handle them after model pruning, helping reduce dependence on the cloud in cost-sensitive scenarios. Combined with GigaDevice’s humanoid robot solution page (a “perception—decision—control—actuation” architecture, with MCU, memory, and analog chip combinations covering dexterous hands, joint modules, IMUs, power management, etc.), this illustrates its domestic MCU positioning of “Arm + RISC-V dual architecture + robotics/edge AI.” This item is interview-based content with no new product launch, included as a strategic observation.

III. Domestic Team Updates and Deep Dives

3.1 SpacemiT: Next-Generation Coherent Interconnect Bus N200 Completed, Forming Three Major Segments of General Computing + Intelligent Computing + Interconnect (released 09-07, backfilled in this issue)

Date: 2026-09-07 (company release; missed in the previous two windows, backfilled in this issue)　Source: SpacemiT official website news, GitHub spacemit-com/model_zoo_rl, spacemit-com/ai-sdk

SpacemiT disclosed on its official website that its next-generation self-developed high-performance coherent interconnect bus N200 has officially completed development. Following its layout of general-purpose computing CPU cores (X60/X100/X200) and intelligent computing AI cores (A60/A100/A200), the completion of N200 marks the finalization of its three core technology segments: “general computing, intelligent computing, and computing interconnect”; N200 will be used together with the general computing core X200 and the intelligent computing core A200 in its next-generation computing chip, with mass production expected in 2027. This is an architectural deepening move following K3 (the world’s first mass-produced RISC-V AI CPU compliant with the RVA23 specification, 60 TOPS, supporting on-device inference for 30 billion to 80 billion parameters): a self-developed interconnect bus means its next-generation chip will shift from “adopting off-the-shelf NoC” to full-stack self-development, directly supporting multi-core coherence and AI core collaboration bandwidth. On the GitHub side within the window, SpacemiT (spacemit-com)’s on-device AI toolchain continued to iterate: ai-sdk updated the rl/vision submodules multiple times on 09-09 at 14:01 and 17:45, and at 00:22 the next day (Beijing time); model_zoo_rl merged feat(rl): support inference cancellation and YAML provider selection (#11) on 09-09 at 20:19; model-zoo-vision, docs-ai, and linux also had pushes. The RL model zoo and features such as inference cancellation and YAML provider selection correspond to the practical needs of robotics and embodied scenarios for interruptible inference and multi-backend switching. (Note: the company’s news page also lists items in the same batch such as K3 running DeepSeek Harness and exhibiting at GIS 2026; the corresponding events all fall in earlier windows and are not re-included.)

3.2 Nuclei: UK Media Reviews Quintauris RISC-V Ecosystem Collaborations, Nuclei Automotive-Grade IP Aligns with RT-Europa (English media review 09-08~09, collaboration itself from H1 2026)

Date: 2026-09-08 (Electronics World review article; New Electronics reported on the same topic on 09-09)　Source: Electronics World, Automotive World, Quintauris newsroom, Nuclei announcement (2026-06-16)

UK media outlet Electronics World published a review article on 09-08, with New Electronics following on the same topic on 09-09: Quintauris is expanding its RISC-V ecosystem through sustained collaborations, adding four partnerships in H1 2026—Elektrobit (04-21, automotive software, serving software-defined vehicles), Nuclei (06-16, automotive-grade RISC-V processor IP aligned with the Quintauris RT-Europa real-time platform specification), Ashling (debug and development tools), and the EM-Altair Profile specification, covering software, hardware, and toolchain. The core of the Nuclei portion is: RT-Europa is the first platform specification for automotive real-time RISC-V processors (defining deterministic memory access, interrupt handling, privilege modes, physical memory protection, debug interfaces, and SoC integration requirements), with which Nuclei aligns its production-validated NA series; the Nuclei NA series is the world’s first RISC-V processor IP to pass ISO 26262 ASIL-D certification, covering ASIL-A through ASIL-D, with more than 300 customers, applied in LiDAR, millimeter-wave radar, domain controllers, automotive-grade MCUs, automotive Ethernet, and SoC safety islands. It must be made clear: this item is an English-media review-style re-report of existing collaborations, and the collaborations themselves all occurred in H1 2026 (not new events in this window); its value for inclusion lies in once again amplifying the industry signal that “Chinese RISC-V IP has entered an international automotive-grade reference platform”; within the window, the 42 repositories in the Nuclei-Software GitHub organization had no pushes, and there was no independent development activity.

3.3 Comprehensive Window Observations: DAMO XuanTie Hypervisor Za* Tests Merged into Statistics Script, Sophgo SG2044 UEFI and Sipeed NanoKVM Routine Iterations (09-09)

Date: 2026-09-09　Source: XUANTIE-RV/damo-rv-priv-ats commits, sophgo/sophgo-edk2, sipeed/NanoKVM, espressif org

DAMO XuanTie’s public repository damo-rv-priv-ats merged #29 Add Hypervisor Za* atomic suites into run_case_stats.sh on 09-09 at 10:17 (Beijing time) (author and commit time same day), incorporating the Hypervisor atomic instruction (Za*) test suites added on 09-07 into the test case statistics script, continuing the pace of verification system reinforcement from the sail integration into GitHub Actions on 09-08; this is test infrastructure improvement; the extension specification repository thead-extension-spec had no new commits within the window (the most recent being the L1 qualification of XTheadCmo on 09-07). Sophgo’s UEFI boot side had routine updates: sophgo-edk2 merged SG2044: Update external-modules/unicorn and MultiArchUefiPkg on 09-09 at 21:27, with MultiArchUefiPkg and unicorn-for-efi pushed in the same batch, continuing the edk2-platforms update from 09-08, iterating around SG2044 platform firmware. Sipeed’s NanoKVM had a push on 09-09 at 16:38 (RISC-V IP-KVM device repository, routine evolution). Espressif was the most active organization on GitHub among domestic teams in the window, with 41 repositories pushed, covering esp-idf, esp-matter, connectedhomeip, esp-brookesia (UI framework), esp-dl, esp-rainmaker-neo, llvm-project, and gcc mirrors, consistent with the high-frequency evolution of its RISC-V wireless MCU (ESP32-C, ESP32-H series) ecosystem. Nuclei (Nuclei-Software) and ESWIN Computing (eswincomputing) were silent within the window. Conclusion: there were no release-level updates from domestic teams in this window; the substantive content consists of the aforementioned commits and the newly backfilled N200 interconnect bus.

IV. Special Chapter on Embodied Intelligence and Robotics

4.1 Shenzhen IICIE Day 1: RISC-V Industry Ecosystem Innovation Conference Agenda and Exhibitor Lineup Confirmed, On-site Coverage Pending (09-09)

Date: 2026-09-09 (exhibition opening day; as of 08:18 in this window, no on-site reports yet)　Sources: IICIE 2026 RISC-V Industry Ecosystem Innovation Conference official agenda page, IICIE Conference List, IICIE pre-show report (Sohu/Kanchaiwang), Global Semiconductor Watch pre-show article

The Shenzhen IICIE International Integrated Circuit Innovation Expo is being held from 09-09 to 11 at the Shenzhen World Exhibition & Convention Center (Bao’an), Halls 14 to 16, running concurrently and co-located with CIOE (China International Optoelectronic Exposition) and elexcon Shenzhen International Electronics Show (the three shows have a total exhibition area of 320,000 square meters and more than 5,000 exhibitors; IICIE itself covers about 60,000 square meters with over 1,100 exhibitors). The expo features a “RISC-V Ecosystem Application Showcase Zone” (created by IICIE in partnership with Manhua IC and IC TIME), gathering domestic RISC-V companies including DAMO XuanTie, Sophgo, CCore Technology, SpacemiT, and Zhongde Industrial, to showcase processor IP, high-performance computing chips, software and hardware platforms, and full-scenario deployment solutions; the pre-show article explicitly states that open-source architecture benchmarks such as the “DAMO XuanTie series chips” will appear in the AI+ featured zone and the RISC-V zone. RISC-V-related sessions are concentrated on the afternoon of 09-09: from 14:00 to 17:00, the “2026 RISC-V Industry Ecosystem Innovation Conference” (theme: “Open Computing, Building the Future Together,” organized by IICIE, Manhua IC, and IC TIME) will be held on the 2nd floor of Hall 14, Room 14C. The agenda features Yan Lingxiao, CEO of Qingxin Zhiyan, on “AI Empowering Digital Chip Design and Verification”; Wang Yulin, Deputy General Manager of the Cloud AI Chip Business Unit at CCore Technology, on “AI + Quantum Security: Building a New Foundation for Cloud-Edge-Device Intelligent Computing”; Kang Xiaoxiao, Vice President of RISC-V Products at Sophgo, on “High-Performance RISC-V Industry Application Practice”; Zeng Yi, Founder and CEO of Sunzhan Technology, on “RISC-V Driving Edge AI Deployment”; Peng Huacheng, Marketing Director at SpacemiT, on “RISC-V Strong Chips Empowering Ubiquitous Intelligent Connectivity”; Wei Jian, CTO of Xinji Infinite, on “RISC-V from In-Vehicle to Edge”; and Ni Daojun, Executive President of Zhongde Industrial Technology, on “Fraunhofer IPMS RISC-V Processor IP Core Technology Innovation and Global Industry Development Trends,” followed by an open exchange session. On the same day, the “2026 Embodied Intelligence Industry Conference — From Computing Power to Execution, Building Embodied Intelligence Systems” will be held in the in-hall meeting room of Hall 15. Limitations: As of the close of this report window, neither Chinese nor English search channels have yielded on-site reports, speech highlights, or new product announcement releases from the first day of the conference (the Google News channel was unavailable in this window, and a switch to Tavily search still yielded nothing). Therefore, this item can only confirm the agenda and exhibitor lineup; given the dense afternoon agenda on the opening day and the concentrated participation of domestic teams, conference outcomes are expected to be released in a concentrated manner after channel indexing on 09-10, and tomorrow’s report will follow up with priority.

V. Summary and Trend Observations

In this reporting window, news coverage was relatively weak while open-source activity was robust. Domestically, the industry has entered a transitional state on the first day of the exhibition — “agendas landing, on-the-ground developments yet to unfold.” Key points are summarized as follows:

First, open-source cores are entering a period of structural restructuring. After rolling out new vector backend instruction surfaces over three consecutive days (whole-register moves, vfma/widen, VIDiv), XiangShan removed the VFAlu/VFMA wrapper layer on 09-09 and switched to direct generation via configuration. This was accompanied by the release of XiangShan-Dashboard 1.0.0, a difftest FPGA probe fix, and the addition of a Zicfilp template to XiangShanLab — demonstrating that verification and toolchain support are advancing in sync. DAMO XuanTie merged Hypervisor atomic-class instruction tests into its statistics scripts, continuously solidifying its test baseline. Signal quality on the open-source side exceeds that on the news side.

Second, the RISC-V edge segment has formed a dual-track product narrative of “wireless connectivity + robot control.” The ESP32-C5 (dual-band Wi-Fi 6 RISC-V SoC) is spreading toward Pico-compatible form factors via Waveshare boards, lowering the barrier to entry for developers. GigaDevice, combining GD32’s Arm+RISC-V dual architecture with EtherCAT deterministic control and Cortex-M7/M33 edge inference, has brought RISC-V into its robot/industrial control product matrix.

Third, domestic teams are advancing architectural depth. SpacemiT completed development of its N200 self-developed coherent interconnect bus, filling out the three major blocks of “general-purpose compute core + AI compute core + interconnect bus,” pointing toward full-stack self-development for its next-generation chip targeted at 2027 mass production. On the GitHub side, iterations to its RL model library, interruptible inference, and multi-backend selection features directly address embodied intelligence scenario requirements. Nuclei’s automotive-grade IP was again mentioned in an international media roundup, reflecting that Chinese RISC-V IP continues to be embedded in international automotive-grade reference platforms (the collaboration itself dates to H1 2026, not a new event).

Fourth, the exhibition window has opened but on-the-ground developments have yet to arrive. On the first day of IICIE Shenzhen, the RISC-V Industry Ecosystem Innovation Conference agenda (seven talks from Qingxin Zhiyan, NationalChip, Sophgo, Sunlitor, SpacemiT, Chipverse, and Sino-German Industry) landed alongside the “Embodied Intelligence Industry Conference,” with DAMO XuanTie, Sophgo, SpacemiT, and others exhibiting in a concentrated fashion. First-day on-site reports and announcements have not yet been indexed by retrieval channels within this window, making follow-up tracking highly valuable.

Limitations: External retrieval channels in this window (Google News RSS and related GitHub channels) remained unreachable (the 08:19 collection was the last successful one). This issue was substituted with direct connections to api.github.com and Tavily searches. Google News-style supplementary searches for Chinese teams and routine queries for English-language vendors (SiFive/Andes/StarFive/Milk-V/SpacemiT/SOPHGO) could not be executed per the established protocol, so there is a possibility of missed items. Under GitHub’s unauthenticated API rate limits, org checks sampled active repositories sorted by pushed_at; non-default-branch pushes and low-activity repositories may have been missed. Commit content from XiangShan, XuanTie, Sophgo, and others was judged solely on commit messages without code-by-code verification. The SpacemiT N200 item was company-released on 09-07 and missed in the previous window; it is belatedly included here with a note. The Nuclei and Quintauris content is a 09-08 English-media retrospective on an H1 2026 collaboration, noted in the body as not a new event.

Appendix: Source Verification Table and Complete Source List

Source / Query Verification Result
fetch_news.py comprehensive collection (HN, gnews, CNX/LinuxGizmos/Phoronix RSS, GitHub topic search, 24h window, last successful collection) 11 candidates, 3 included (Waveshare ESP32-C5 Pico, GigaDevice podcast, Quintauris ecosystem review related leads). Excluded: grain project x2 (same name, not a RISC-V OS); Ethereum Vitalik recursive STARK memory pool EIP, a16z Crypto rewriting Jolt post-quantum (crypto/zkVM topics, RISC-V only a underlying concept, not an event); YuzukiNeko Allwinner F101 (RS Web Solutions 09-09 repost, already detailed in 09-08 report 2.1, echo not re-included); Canonical Hot Chips talk (ServeTheHome original date 09-07, already detailed in 09-08 report 1.1, HN 09-09 repost)
GitHub API org pushed verification (XUANTIE-RV/Nuclei-Software/openxiangshan/sophgo/spacemit-com/sipeed/eswincomputing/espressif, direct connection 30h window) openxiangshan 16 repo pushes included (1.1); XUANTIE-RV priv-ats 09-09 push included (3.3); sophgo 3 repos, spacemit-com 5 repos, sipeed 1 repo, espressif 41 repo pushes included (2.1/3.1/3.3); Nuclei-Software, eswincomputing silent (0 pushes)
GitHub commits verification (XiangShan, damo-rv-priv-ats, thead-extension-spec, spacemit-com/ai-sdk, model_zoo_rl, sophgo/sophgo-edk2, openxiangshan org commit search) XiangShan VFAlu/VFMA refactor, JAL/JALR fix, I2F fflags, emu CI included (1.1); priv-ats #29 included (3.3); thead-extension-spec no in-window commits (most recent 09-07); spacemit model_zoo_rl #11, ai-sdk submodule update included (3.1); sophgo-edk2 SG2044 UEFI included (3.3)
Tavily search (IICIE/Shenzhen Integrated Circuit Innovation Expo/RISC-V Industry Ecosystem Innovation Conference/Embodied Intelligence Industry Conference/DAMO XuanTie/SpacemiT/Quintauris Nuclei/vendor English names, multiple sets) Retrieved IICIE official RISC-V conference agenda page (2026RISC-V.html, containing seven talks and speakers), pre-show lineup (DAMO XuanTie/Sophgo/NationalChip/SpacemiT/Sino-German Industry); IICIE first-day on-site report not obtained (channel not indexed); SpacemiT N200 (09-07); Quintauris ecosystem review (Electronics World 09-08, New Electronics 09-09, Automotive World), based on which traced and confirmed the two Nuclei announcement dates as 2025-11-10 and 2026-06-16 (both from this window, only media reviews included)
Original site crawl verification (spacemit.com/news, nucleisys.com, quintauris.com, gigadevice.com, cnx-software.com, servethehome.com, chinaflashmarket.com) spacemit news page verified N200 (09-07 10:54) and DSH-K3 (09-07 11:02) entries; nucleisys announcement page verified RT-Europa collaboration date 2026-06-16; cnx-software verified ESP32-C5 Pico full specs and four versions; servethehome original date 09-07 (confirming Canonical entry as yesterday’s echo); chinaflashmarket XuanTie E901 article verified as 2025-08-27 old article (search snippet mixed in unrelated stock content, excluded)
External search channel status verification 08:19 collection successful; from 08:20 onward multiple consecutive probes (news.google.com / api.github.com / www.google.com) all timed out; subsequent probes also timed out. Direct connection to www.baidu.com / www.bing.com / github.com normal (200), api.github.com direct connection available (adopted)

Complete Source List: Hacker News, CNX Software, Open Source For You, ServeTheHome, Electropages, Electronics World, New Electronics, Automotive World, Quintauris official website and newsroom, GigaDevice official website, Nuclei (Nuclei Technology) official website, SpacemiT official website, Waveshare documentation site, IICIE official agenda page (iicieexpo.com / semi-e.com), Global Semiconductor Watch (dramx.com), Sohu/Kancha Network, CFM Flash Market (for verification), GitHub API (orgs repos / commits / search commits, direct connection), Tavily search backend, etc.

This report is automatically generated by the Hermes daily scheduled task. The report begins with a traditional index; body entries are organized by open-source community and software ecosystem, product and ecosystem developments, domestic team developments and deep dives, and a special chapter on embodied intelligence and robotics. Due to external search channel failure in this window, the Google News collection channel was unavailable, and direct GitHub API and Tavily search were used as substitutes.