RISC-V Daily Intelligence Report (2026-09-09)
Research window: Past 24 hours (2026-09-08 08:18 ~ 2026-09-09 08:18, Beijing Time) Sources: HN, Google News aggregation, CNX Software, ServeTheHome, Science and Technology Daily / Shangguan News and other domestic media, GitHub API (org repo pushed and commit search), etc. (see appendix source verification table for details)
Issue Index
- I. Open Source Community and Software Ecosystem
- XiangShan: New vector backend merged with VIDiv support, storage queue fixes and verification repo batch pushes (09-08)
- Open source hardware demo: Baochip-1x performs full on-chip GPT training without FPU, hits HN (09-08)
- II. Product and Ecosystem Developments
- Midea partners with Shanghai HiSilicon to launch “Jingwei A²MCU” edge AI smart refrigerator: self-developed RISC-V core lands in white goods (09-08)
- III. Domestic Team Developments and Deep Dives
- SJTU IPADS-led SPMP memory protection extension officially merged into RISC-V international standard, first ISA feature fully led by a domestic team (news 09-08, approved 08-31)
- Science and Technology Daily publishes report on Tibet’s first RISC-V thousand-card computing cluster: Ximu Computing STCP950L supports 671B-class models (report 09-08, cluster delivered 2026-04)
- Comprehensive window observation: DAMO XuanTie sail CI integration, sophgo/spacemit/sipeed routine iterations (09-08)
- IV. Embodied Intelligence and Robotics Special Chapter
- Window observation: Shenzhen IICIE opens today, RISC-V Industry Ecosystem Innovation Conference and Embodied Intelligence Industry Conference begin this afternoon (09-09)
- V. Summary and Trend Observations
- Appendix: Source Verification Table and Complete Source List
I. Open Source Community & Software Ecosystem
1.1 XiangShan: New Vector Backend Merges VIDiv Support, Store Queue Fix and Batch Pushes to Verification Repos (09-08)
Date: 2026-09-08 (15:47–19:30 Beijing time batch) Source: GitHub openxiangshan/XiangShan commits
The feature build-out of the new vector backend for the XiangShan open-source high-performance core (Kunminghu) continues: the 09-08 batch merged feat(VIDiv) “support VIDiv”, adding integer division instruction support to the vector execution path; the same batch’s fix(StoreQueue) addresses unexpected uncacheMove caused by vector inactive elements (#6474). Combined with the 09-06 whole-register move and the 09-07 vfma/vfmac floating-point multiply-add and widen instruction batches, it is clear the new vector backend is rapidly expanding its instruction coverage in the order of “register moves — floating-point multiply-add — integer division — subsequent matrix/reduction operations.” On the same day, verification and tooling repos under the openxiangshan org saw batch pushes: NEMU (16:27), XSAI (batch around 00:26, pushed 16:26 UTC), difftest (15:27), gsim, XSCache, XiangShan-Dashboard (23:42), and GEM5 all showed pushed signals — routine iterations of the supporting verification environment, with no version releases. On the engineering side, XiangShan has entered a period of high-frequency vector subsystem development; continued tracking of its new vector backend merge cadence is recommended.
1.2 Open Hardware Demo: Baochip-1x Trains a Full GPT On-Chip Without an FPU, Hits HN (09-08)
Date: 2026-09-08 (HN front page 21:49 Beijing time; original post 09-04) Source: Hacker News, rvembedded original post, GitHub AI-from-Scratch-in-C
Embedded engineer Armstrong Subero published a demo: within his Rovari education platform ecosystem, he fully ported the GPT training program from his “AI from Scratch in C” course manuscript to run on Baochip-1x (Dabao evaluation board, shipping via Crowd Supply), the open-source chip designed by bunnie Huang. Baochip-1x is a 22nm “mostly open” RISC-V SoC: a 350 MHz RV32IMAC core, no FPU (no F extension), no Flash, 4 MB ReRAM for executable code + 2 MB SRAM. The demo model is a 27,680-parameter decoder-only transformer (vocab 28, d_model 32, 2 layers, 4 heads, context 64), including full backpropagation, the Adam optimizer, and gradient checking; the entire package plus the soft-float runtime is only 37 KB, with a training working set of about 1 MB (activation cache occupying 426 KB). On-chip training from random weights takes about 1 hour, with weights finally written to ReRAM; every floating-point multiply-add is performed by software floating-point emulation (about 4.6 million per step). The post demonstrates three points: on-device training of a “minimal viable GPT” is feasible on an FPU-less MCU; ReRAM has already been commercially deployed as a Flash replacement on 22nm; and open-source chips paired with open-source teaching materials can reproduce frontier concepts. It hit the HN front page on the evening of 09-08 (weakly trending); the content has high educational value and is included as an observation on open hardware and edge AI education.
II. Product & Ecosystem Developments
2.1 Midea and Shanghai HiSilicon Launch “Jingwei A²MCU” Edge-AI Smart Refrigerator: In-House RISC-V Core Lands in White Goods (09-08)
Date: 2026-09-08 (disclosed by Kuaikeji at 18:48) Source: Kuaikeji, HiSilicon official Hi3066M product page
HiSilicon disclosed on 09-08 a jointly developed edge-AI smart refrigerator solution with Midea: powered by the “Jingwei A²MCU” chip series, it achieves 9.6% overall energy savings via on-device AI reinforcement learning. Under the new refrigerator energy-efficiency national standard implemented in June (for 500L side-by-side models, Tier-1 daily power consumption drops from 0.92 kWh to 0.55 kWh, with the entry threshold raised 30%–40%), a single unit can save about 19.3 kWh per year. Jingwei A²MCU is HiSilicon’s MCU series for air conditioners, refrigerators, washing machines, and kitchen white goods, based on an in-house RISC-V core (models on sale on HiSilicon’s site such as Hi3065H/Hi3066M: 200 MHz 32-bit RISC-V + FPU, built-in eAI engine, 512 KB Flash / 64 KB SRAM). The eAI engine is optimized specifically for edge-side energy-saving algorithm operators, enabling the reinforcement learning policy to run in real time on the same die as the refrigerator main controller; the solution adopts a dual-track “edge-cloud collaboration + pure edge-side” approach (offline pre-training + online adaptive fine-tuning) and dual-track “AI main control + PID fallback” protection. With 5 million refrigerators online, this cuts carbon emissions by about 88,000 tons per year. Significance: HiSilicon’s RISC-V MCU + edge AI has scaled into flagship energy-efficiency scenarios at a leading white-goods brand — a benchmark case of “RISC-V entering home appliances” moving from main-control replacement toward edge-side intelligence, resonating with the white-goods energy-efficiency upgrade window driven by the new national standard in June.
III. Domestic Team Updates and Deep Dives
3.1 SPMP Memory Protection Extension Led by SJTU IPADS Formally Merged into RISC-V International Standard, China’s First Fully Led ISA Feature (News 09-08, Approved 08-31)
Date: 2026-09-08 (concentrated coverage by Wenhui/Shangguang and others; standard approved 08-31) Source: Shangguang News/Wenhui Daily, Sina Finance reprint
Mainstream Chinese media on 09-08 concentrated on a standards milestone: on 2026-08-31, the SPMP (Supervisor Physical Memory Protection) instruction set standard, led by IPADS (Institute of Parallel and Distributed Systems, Prof. Chen Haibo’s team) at Shanghai Jiao Tong University’s School of Computer Science, formally passed review by the RISC-V International Board of Directors (BoD) and was merged into the RISC-V Instruction Set Architecture (ISA) standard. This is the first ISA standard feature since RISC-V International’s founding in 2015 to be initiated from scratch and fully led by a mainland Chinese team: the team submitted the initial architecture draft to the community on 2019-09-23, and after nearly 7 years (over 2,500 days) of technical review and proposal revision, the working group chair at the time of approval was IPADS PhD Yang Bicheng. SPMP provides supervisor-mode physical memory protection and isolation capabilities for processors, filling a gap in RISC-V’s security architecture. Significance: this is the first time a domestic institution has held complete leadership “from proposal to finalization” in RISC-V extension standard-setting, marking a shift for Chinese teams from passively following rules to participating in defining them, and accumulating paradigm experience for subsequent domestic RISC-V security features (such as various isolation/confidential computing extensions) entering international standards. This report had not previously covered this event (missed in the window around the approval date of 08-31); it is now added following mainstream media coverage.
3.2 Science and Technology Daily Publishes Report on Tibet’s First RISC-V Thousand-Card Computing Cluster: Stream Computing STCP950L Supports 671B-Class Models (Reported 09-08, Cluster Delivered 2026-04)
Date: 2026-09-08 (published by Science and Technology Daily; cluster actually delivered and operational in 2026-04) Source: Science and Technology Daily/China Science and Technology Network, Tibet Autonomous Region Government Website (first published 2026-04-08)
Science and Technology Daily published on 09-08: China Mobile Tibet, together with Stream Computing, successfully delivered and officially launched Tibet’s first thousand-card RISC-V architecture computing cluster in Lhasa, filling the gap in domestic RISC-V high-end computing power in high-altitude regions, as part of China Mobile Tibet’s implementation of the autonomous region’s “Computing Everest” strategy. The cluster is built on Stream Computing’s self-developed STCP950L NPU AI compute cards, taking only 20 days from shipment, deployment and power-on to test acceptance, with 30 days of stable trial operation, and has supported deployment of large models from 7 billion to 671 billion parameters, fully adapted to batch inference, real-time AI services, and large-model agent scenarios; it focuses on serving three major areas: smart government affairs (accelerating “one-stop government services”), industrial digitalization (specialty agriculture, cultural tourism), and livelihood services (telemedicine, smart education). Note: upon tracing, the cluster’s delivery and operational information was first reported by Tibet Daily on 2026-04-08 (not covered by this report system at the time); this entry entered the window due to Science and Technology Daily’s re-publication, and constitutes an authoritative media restatement of an already-implemented project, with the core increment being the validation conclusion of “long-term stable operation in ultra-high-altitude extreme environments.” Significance: high altitude, low air pressure, and large temperature differentials impose stringent requirements on computing hardware stability; the large-scale deployment of thousand-card-level domestic RISC-V AI computing power in such special scenarios provides extreme-environment empirical evidence for RISC-V entering intelligent computing infrastructure.
3.3 Comprehensive Window Observation: DAMO XuanTie sail CI Integration, sophgo/spacemit/sipeed Routine Iterations (09-08)
Date: 2026-09-08 Source: XUANTIE-RV/damo-rv-priv-ats commits, sophgo/zsbl, spacemit-com/docs-ai, sipeed/maix_ax620e_sdk and other commits APIs
Domestic teams’ GitHub activity on Wednesday evening was all routine development, with no release-level updates: DAMO XuanTie’s public repository damo-rv-priv-ats merged “add sail in github action” (#28) at 11:29 on 09-08, integrating sail (the RISC-V formal semantics simulator) into GitHub Actions, continuing the verification system reinforcement pace of adding Hypervisor Za* tests on 09-07, as part of specification test infrastructure construction; Sophgo’s zsbl and sophgo-edk2 pushed around 14:19 and 20:20 respectively, routine iterations of UEFI/boot toolchain; SpacemiT’s docs-ai (19:13), docs-chip (10:28), and llama.cpp fork (11:14, upstream synchronization in nature) had pushes, all documentation or synchronization updates; Sipeed’s maix_ax620e_sdk and its kernel/msp, MaixCDK pushed in a batch from 11:54 to 12:10, routine evolution around the AX620E SDK. Nuclei-Software, eswincomputing, and revyos were silent within the window. Conclusion: no new increments on the domestic team news side; substantive activity is mainly the above GitHub commits, and activity is expected to heat up tomorrow as the IICIE exhibition window begins.
IV. Embodied Intelligence and Robotics Special Chapter
4.1 Window Observation: Shenzhen IICIE Opens Today, RISC-V Industry Ecosystem Innovation Conference and Embodied Intelligence Industry Conference Kick Off This Afternoon (09-09)
Date: 2026-09-09 (opens today; as of 08:18 in this window, no immediate first-day coverage yet) Source: IICIE Conference List, IICIE Official Agenda Page
The Shenzhen IICIE (International Integrated Circuit Innovation Expo) previewed in yesterday’s report opens today (09-09~11) at the Shenzhen World Exhibition & Convention Center (Bao’an), running concurrently and co-located with CIOE China Optoelectronic Expo and elexcon Shenzhen International Electronics Fair, with a total exhibition area of 320,000 square meters and over 5,000 exhibitors. RISC-V-related agenda is concentrated this afternoon: the “2026 RISC-V Industry Ecosystem Innovation Conference” in Hall 14, 2nd Floor, 14C, and the “2026 Embodied Intelligence Industry Conference—From Computing Power to Execution, Building Embodied Intelligence Systems” in the Hall 15 in-hall meeting room, kicking off concurrently; DAMO XuanTie, Sophgo, SpacemiT, ZTE Microelectronics, Beijing Junzheng, and others are on the official exhibitor list, with a “RISC-V Ecosystem Application Showcase Area” and AI+ featured showcase area in the exhibition zone. Yesterday’s report already previewed that “XuanTie/Sophgo/SpacemiT are exhibiting, and from today we enter the observation window for domestic RISC-V x embodied intelligence developments”; within this window (as of 08:18 today), there is no on-site first-day coverage or new product release information, and conference outcomes will be followed up in tomorrow’s report.
V. Summary and Trend Observations
This report window is the eve of a rebound in event density: on the news side, one international standards milestone and two computing-power deployment reports appeared; the open-source community and domestic teams’ GitHub continued routine iterations; and the embodied intelligence direction entered the fulfillment window of the Shenzhen exhibition opening today. Key points summarized as follows:
First, standard leadership achieved a “zero breakthrough.” The SPMP memory protection extension led by SJTU IPADS passed RISC-V International Board of Directors review and was merged into the ISA standard on 08-31, the first ISA feature fully led by a domestic team from proposal to finalization (submitted in 2019, nearly 7 years of effort), receiving concentrated mainstream media coverage from Wenhui/Shangguang and others on 09-08. The narrative around security architecture and “defining the rules” discourse is heating up in tandem, and is expected to drive more domestic security/isolation extension proposals toward international standards at an accelerated pace.
Second, RISC-V computing-power deployment shows “high-end computing power + edge-side white goods” polar cases. Stream Computing’s STCP950L thousand-card cluster operates stably long-term in Tibet’s ultra-high-altitude environment (re-published by Science and Technology Daily on 09-08, supporting 671B-class models), validating the extreme-environment reliability of RISC-V intelligent computing infrastructure; HiSilicon Jingwei A²MCU, with its self-developed RISC-V core + eAI engine, enters Midea refrigerator edge-side energy-saving scenarios (comprehensive energy savings of 9.6%), leveraging the June new national standard window to achieve large-scale deployment of “RISC-V + edge-side AI” in a leading white goods manufacturer.
Third, open-source processor engineering pace continues. XiangShan’s new vector backend pushed vfma/widen (09-07) and VIDiv, StoreQueue fixes (09-08) on consecutive days, with the vector subsystem entering a high-frequency feature-completion period; DAMO XuanTie’s priv-ats integrated sail formal semantics testing into CI, continuously strengthening the verification system; overseas open-source cores such as CVA6 and OpenSBI were basically silent within the window, with XiangShan/XuanTie constituting the currently most active open-source signal sources.
Fourth, the event window opens. IICIE Shenzhen opens today, with the RISC-V Industry Ecosystem Innovation Conference and Embodied Intelligence Industry Conference held this afternoon, and DAMO XuanTie/Sophgo/SpacemiT exhibiting in a concentrated manner; domestic RISC-V x embodied intelligence developments enter a dense release period in the middle of this week, and tomorrow’s report will focus on following up on first-day releases and speech highlights.
Limitations note: Under GitHub’s unauthenticated API rate limits, org checks sampled recently active repositories sorted by pushed_at, and non-default-branch pushes and low-activity repositories may be missed; cva6 had a pushed signal at 23:10 on 09-08 but no new commits on the default branch within the window, suspected to be a branch or tag push, and was not included in the main text; XiangShan/XuanTie commit content is judged only by commit messages; the Tibet cluster entry’s event itself occurred in 2026-04, and this is a media re-publication follow-up, noted in the main text; the SPMP approval date (08-31) is earlier than this report’s window, and it is included and traced per the “mainstream media report date 09-08.”
Appendix: Source Verification Table and Complete Source List
| Source / Query | Verification Result |
|---|---|
| fetch_news.py comprehensive collection (HN, gnews, CNX/LinuxGizmos/Phoronix RSS, GitHub topic search, 24h window) | 10 candidates, 1 included (Baochip GPT HN, 1.2). Excluded: YuzukiNeko (appeared across CNX/HN/开源中国 on the same day, already covered in detail in yesterday’s report 2.1, echo not re-included); Canonical enterprise readiness HN re-share (already covered in detail in yesterday’s 1.1); Show HN m68000/Z80 browser IDE (not RISC-V); grain project x2 (same name, not a RISC-V OS); NVIDIA Hot Chips six talks (GPU topic); GlobalFoundries MIPS Acies (MIPS, not RISC-V) |
| Google News English supplementary search (RISC-V when:1d, SiFive when:3d, Andes when:7d, StarFive/Milk-V, SpacemiT, SOPHGO, RISC-V Summit when:7d) | RISC-V when:1d yielded 5 additional hits, all excluded (MIPS, NVIDIA, CACM general piece on European tech sovereignty, Ubiquiti switch review, Arm CSS mobile platform); SiFive/Milk-V+StarFive/SOPHGO/RISC-V Summit 0 hits; Andes only 09-02 ChipAgents collaboration and 09-04 weekly roundup (outside window) |
| Google News Chinese supplementary search (RISC-V when:3d, XiangShan processor, XuanTie, SpacemiT, ESWIN, StarFive, GigaDevice, IICIE, etc. when:7d) | RISC-V when:3d yielded three substantive reports, all traced and included: Tibet thousand-card cluster (3.2), Midea Jingwei refrigerator (2.1), SJTU SPMP standard (3.1); noise excluded: sports “百变大咖秀” SEO piece, RFID World salon registration, 信息化观察网 industry analysis (no event). XiangShan processor hits were the SPMP trio (XiangShan project background association); SpacemiT only AGIC wrap-up and other out-of-window old news; StarFive/ESWIN/GigaDevice hits had no direct connection to RISC-V events (EDA trends, general finance) |
| web_search (Tavily) tracing verification | 上观/文汇报 original text verified SPMP details (submitted 2019-09-23, approved by BoD 08-31, Yang Bicheng as working group chair); 快科技 original text verified Jingwei A²MCU (512KB Flash/64KB RAM, eAI engine), HiSilicon official site Hi3066M/Hi3065H corroborated RISC-V core specs; 科技日报 original text verified Tibet cluster, and tracing revealed 西藏日报 2026-04-08 first publication (noted in the entry); IICIE agenda page verified today’s RISC-V Industry Ecosystem Innovation Conference and Embodied Intelligence Industry Conference times and locations |
| GitHub org pushed verification (XUANTIE-RV/sophgo/spacemit-com/Nuclei-Software/sipeed/eswincomputing/openxiangshan/openhwgroup/riscv-software-src/revyos) | openxiangshan multi-repo batch push included (1.1); XUANTIE-RV priv-ats sail CI included (3.3); sophgo zsbl/edk2, spacemit docs-ai/docs-chip/llama.cpp, sipeed maix_ax620e_sdk batch included (3.3); Nuclei-Software/eswincomputing/revyos silent; openhwgroup cva6 pushed at 23:10 but no in-window commits on default branch (not listed); riscv-software-src only sail-riscv-tests pushed |
| GitHub commits verification (XiangShan/CVA6/OpenSBI/priv-ats/thead-extension-spec) | XiangShan VIDiv+StoreQueue #6474 included (1.1); CVA6/OpenSBI/thead-extension-spec no commits in window; priv-ats #28 included (3.3) |
| 国际电子商情 “Ten Chips Look at RISC-V” long-form article | Content is a compilation of ten domestic chips from the 08-13 Dishui Lake Forum (SpacemiT K3, T-Head EA6530, ESWIN EAI8800, Blue Core LX500, StarFive JH-B100, etc.); related reports already covered in each August daily issue, it is an old-news compilation, not listed as an entry |
Complete Source List: Hacker News, Google News RSS aggregation, CNX Software, ServeTheHome, 科技日报/中国科技网, 上观新闻/文汇报, 新浪财经, 快科技, HiSilicon official site, IICIE official agenda pages (semi-e.com / iicieexpo.com), Tibet Autonomous Region Government website, GitHub API (orgs repos / commits), rvembedded.com, domestic tech media, etc.
This report is automatically generated by the Hermes daily scheduled task. The report opens with a traditional index; body entries are organized by Open-Source Community and Software Ecosystem, Product and Ecosystem Developments, Domestic Team Developments and Deep Dives, and Embodied Intelligence and Robotics Special Section.