Research window: Past 24 hours (2026-09-03 08:18 ~ 2026-09-04 08:18, Beijing time) Sources: HN, Google News aggregation, Phoronix, CNX Software, ServeTheHome, Semiconductor Engineering, ncsti.gov.cn (reposted by Beijing Yizhuang official WeChat), GitHub API (org repo and commit search), etc. (see appendix for details)

Index

  • I. Open Source Community and Software Ecosystem
    • GCC 17 merges native RISC-V -mcpu/-mtune=native support (09-03)
    • SiFive details RISC-V standard system and future evolution: Hot Chips 2026 talk transcript addendum (09-03)
  • II. Product and Ecosystem Updates
    • Trend item: CUDA-on-RISC-V media echo continues: BigSky positioned as a “porting validation platform,” NVLink Fusion chips no earlier than 2027 (09-03)
  • III. Domestic Team Updates and Deep Dives
    • XiangShan main repo and XSAI: vector/floating-point unit refactoring advances, AI branch continues syncing (09-03/04)
    • HICOOL 2026 RISC-V+AI Collaborative Innovation Challenge concludes (09-03)
    • Comprehensive GitHub check of domestic teams: overall quiet (09-03/04)
  • IV. Embodied Intelligence and Robotics Special Section
    • Humanoid robot computing moves toward a “centralized + distributed” hybrid architecture, with safety complexity exceeding autonomous driving (09-03)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List

I. Open-Source Community and Software Ecosystem

1.1 GCC 17 Merges Native -mcpu/-mtune=native Support for RISC-V

Date: 2026-09-03　Source: Phoronix

GCC’s long-missing “native auto-tuning” capability on the RISC-V backend has finally been filled in: the previously discussed -mcpu=native / -mtune=native support patch has been merged into GCC mainline and will land with GCC 17.1 (releasing in early 2027). Previously, RISC-V users who wanted code generation optimized for their local CPU had to hand-write specific model names (such as sifive-p550, spacemit-x100), inconsistent with the native behavior on x86/Arm. This patch comes from Kito Cheng of SiFive (one of the core maintainers of the RISC-V toolchain). Known current limitation: for heterogeneous multi-core SoCs (such as mixed SpacemiT A100 and X100 platforms), GCC can only select the CPU target based on the core type on which the compilation process actually runs, and cannot yet perceive the full-chip heterogeneous topology. This is another small step in the RISC-V toolchain’s “serverization/ease-of-use” push, complementing the RVA23 server silicon landing this year (see 1.2).

1.2 SiFive Details the RISC-V Standards System and Future Evolution: Hot Chips 2026 Talk Transcript Supplement

Date: Published 2026-09-02 / picked up by HN and Google News on 09-03 (supplement for this window)　Source: ServeTheHome (on-site notes by Patrick Kennedy), Hacker News

ServeTheHome has belatedly published its on-site notes from Hot Chips 2026 (late August, Stanford) — SiFive’s talk on RISC-V standards and adoption progress. This talk, together with the NVIDIA CUDA-on-RISC-V tutorial already reported on 09-02, belongs to this year’s Hot Chips “RISC-V serverization” narrative; this installment is the more “standards-primer” of the two threads. Key points:

  • Panorama of the standards system: Using RISC-V’s sixteenth anniversary (birthday 2010-05-18) as an introduction, it reiterates that “an open standard is not bound to the fate of a single company”; the four base ISAs (RV32I/RV64I/RV32E/RV64E) have been ratified, and the CHERI capability-security variant and a future RV128 (128-bit address space) are under development;
  • Refinement of the Profile mechanism: Three generations of evolution — RVA20/RVA22/RVA23 (RVA23 ratified in 2024-10, mandating vectors and hypervisor) — clarifying the compatibility model in which major versions add mandatory features while minor versions only add options, ensuring new software can run on old hardware; RVB23 (for Yocto/OpenEmbedded custom build scenarios) evolves independently;
  • AI and security: For matrix extensions, a “1+3” parallel路线 of AME/IME/VME plus a vector fast-track is given; it emphasizes that RISC-V is the only architecture that can simultaneously serve as an AI host ISA (CUDA porting), an accelerator device ISA, and an edge-side self-hosted ISA; the security feature list includes PMP, RISC-V Worlds bus-level isolation, supervisor domains for confidential computing, and pointer masking, with in-progress projects including CHERI, speculation barriers, memory tagging, and memory encryption contexts;
  • Debunking rumors: It responds one by one to claims such as “variable-length instructions are a weakness,” “RISC-V needs instruction fusion to be competitive,” and “RISC-V performance isn’t good enough” (the alarming gnews headlines like “SiFive RISC-V requires Fusion” and “has too many extensions” all come from subsections of this article). The author concludes: the first RVA23 server ships this year, a real signal that the standards work is landing in hardware.

II. Product and Ecosystem Developments

Date: 2026-09-03　Source: igor’sLAB (German media, English edition)

German outlet igor’sLAB published a follow-up interpretation of the SiFive BigSky SF-2U870 on 09-03 (the main event was already reported on 08-25 and is not expanded upon again here); its framing can serve as third-party confirmation of the ecosystem’s pace: BigSky (32-core P870-D @ 2.0GHz, RVA23, Ubuntu 26.04 LTS / RHEL 10) is positioned as a porting validation platform for hyperscale cloud vendors, chip companies, and software developers, rather than a production server competing with EPYC/Xeon; CUDA already runs on it — the RISC-V cores serve as the host running the operating system and control tasks, while CUDA kernels actually execute on the NVIDIA GPU; according to the RISC-V International weekly, this demonstration was a RISC-V host + NVIDIA Blackwell GPU combination. The article reiterates: SiFive and NVIDIA are advancing NVLink Fusion integration, and the first custom RISC-V chips integrating NVLink Fusion may not appear until 2027 at the earliest; BigSky’s significance lies in preparing the software stack on real hardware first. Combined with NVIDIA’s requirement list already reported on 09-02 (RVA23/ACPI/coherency), the judgment on the pace of “CUDA on RISC-V” remains unchanged: software first, silicon later.

III. Domestic Team Updates and Deep Dives

3.1 XiangShan Main Repo and XSAI: Vector/Floating-Point Unit Refactoring Advances, AI Branch Continues to Sync

Date: 2026-09-03/04　Source: openxiangshan/XiangShan commits, openxiangshan/XSAI, openxiangshan organization

The open-source high-performance core XiangShan, led by the Institute of Computing Technology, Chinese Academy of Sciences, merged 6 commits in the window (a slowdown from 10+ yesterday, within normal fluctuation), concentrated on vector/floating-point execution and pipeline optimization:

  • refactor(VCVT): Refactoring of the floating-point and vector type conversion unit (VCVT) has begun, introducing a new VCVTWrapper structure (initial support);
  • perf(LoadQueueReplay): Optimized LoadQueueReplay latency (#6422);
  • refactor(VIMac): Initial support for the vector integer multiply-add unit; fix(vector,exu): vector execution source operands should not always go through bypass data;
  • config(isa): ISA extension string aligned with implementation (#6463); ready-to-run sync bumped the NEMU reference.

Deep dive: XSAI — the XiangShan AI branch advancing in parallel. Under the openxiangshan organization there is a repository self-described as “A fork of Xiangshan for AI” — XSAI (created 2023-12) — which continued merging within the window: the difftest submodule aligned with mrelease retirement semantics (#121), and the nightly regression checkpoint pool was updated (#120); looking back, it batch-synced Kunminghu (kunminghu-v2) bug fixes on 08-31 (#115) and introduced a commit-stall watchdog for the Palladium simulation environment (#119) — indicating that the XiangShan team maintains a processor variant line targeting AI workloads alongside the general-purpose core (Kunminghu), and keeps it in sync with mainline correctness fixes; another repository, YunSuan, is an independent unit-test project for XiangShan functional units (Verilator simulation), part of the verification infrastructure. Overall, the XiangShan family’s development loop of “processor + simulator + AI variant + functional unit tests” continues at full speed, with vector/floating-point and reliability polishing as the current theme.

3.2 HICOOL 2026 RISC-V+AI Collaborative Innovation Challenge Concludes

Date: 2026-09-03 (finals and awards)　Source: International Science and Technology Innovation Center Network Service Platform (reposted by Beijing Yizhuang official WeChat), competition homepage rdi.hicool.com, Economic Information Daily (semifinal report, 08-21)

China’s first specialized competition focused on RISC-V and AI integrated innovation — the HICOOL 2026 Global Entrepreneurship Competition “Integrated Circuit Frontier Technology: RISC-V+AI Collaborative Innovation Challenge” — completed its finals pitch and awards ceremony at the China International Exhibition Center, concluding successfully after the top ten teams competed for all awards:

  • First prize went to “RISC-V and OpenHarmony-based intelligent video surveillance (NVR) edge AI analysis system”; there were also 3 second prizes and 6 third prizes, with winning projects covering edge AI analysis, domestic chip industrial adaptation, edge computing terminals, education scenario solutions, industrial data stream processing, and other directions;
  • The competition was guided by the Beijing Municipal Talent Work Bureau and hosted by the Beijing Overseas High-Level Talent Association, jointly organized by the Beijing RISC-V Digital Infrastructure Innovation Center and Beijing ESWIN Computing, with the RDI Alliance and others co-organizing; the four tracks were AI-driven chip design, computing foundation and CLI innovation, RISC-V+AI scenario applications, and OPC super-individual lightweight AI;
  • The award benefits design reflects Beijing Yizhuang’s ecosystem playbook: eligibility to apply for up to RMB 20 million per year in computing vouchers, the Economic-Technological Development Area’s “20 Science and Innovation Measures / 10 Talent Measures” and integrated circuit special policies, free use of ACT (RISC-V Architecture Compliance Test) tools and RISC-V test certification, ESWIN Computing ecosystem endorsement and developer ecosystem connections, and free membership in the RDI Alliance.

Compared with the 08-21 semifinals (70+ projects advancing, nearly 100 entrepreneurs), the finals focused on the top ten, marking the competition’s completion of the first leg from “project solicitation” to “incubation and landing.” For the domestic RISC-V ecosystem, this is another visible move of the “open-source core + leading commercial company + regional industrial belt” three-way synergy, following “XiangShan open source, ESWIN commercial, Yizhuang industrial policy”; the first-prize NVR edge AI project hits both RISC-V and OpenHarmony open-source foundations, and its subsequent industrialization is worth tracking.

3.3 Comprehensive GitHub Check of Domestic Teams: Generally Quiet

Date: 2026-09-03/04　Source: XUANTIE-RV, Nuclei-Software, spacemit-com, sophgo, sipeed, starfive-tech, revyos, eswincomputing and other organization repos APIs

A window check of nine domestic RISC-V team GitHub organizations (pushed_at since 09-03 09:00 Beijing time):

  • T-Head (XUANTIE-RV): 0 pushes, continuing the post-release quiet;
  • XiangShan (openxiangshan): see 3.1, most active in the window (13 repos with pushes, 6 commits in the main repo);
  • Nuclei (Nuclei-Software): one each for nuclei-sdk and lauterbach-startup, routine SDK maintenance (the latest merge on the nuclei-sdk default branch is still the June FreeRTOS tick fix; this window’s push appears to be branch activity);
  • SpacemiT (spacemit-com): one each for mpp (multimedia framework), docs-buildroot documentation, and linux kernel sync, routine maintenance;
  • Sophgo: only one for fsbl (boot firmware); Sipeed: sipeed_wiki and maix_ax620e_sdk updates (the picoclaw repo was verified to be a Go toolchain project unrelated to hardware, and excluded);
  • StarFive (starfive-tech), RevyOS, ESWIN Computing (eswincomputing): 0 pushes.

Conclusion: apart from the XiangShan family, domestic teams showed no architecture-level or product-level new developments in the window, consistent with yesterday’s assessment (the post-release quiet period continues). Although ESWIN Computing had no pushes on the GitHub side, it was active on the ecosystem side as a HICOOL co-organizer (see 3.2).

IV. Embodied Intelligence and Robotics Special Section

4.1 Humanoid Robot Compute Moves Toward a “Central + Distributed” Hybrid Architecture, with Security Complexity Exceeding Autonomous Driving

Date: 2026-09-03 (Liz Allan article)　Source: Semiconductor Engineering, Jon Peddie Research analysis (09-03)

Semiconductor Engineering published an industry roundtable review discussing humanoid robot compute architecture and safety design. The core judgments are strongly relevant to the RISC-V ecosystem:

  • Architectural consensus: hybrid. Infineon humanoid robot system architect Ronald Stärz proposed a hybrid model of “central high compute + fingertip/joint-level distributed preprocessing,” explicitly analogizing the automotive migration from centralized ECUs to zone architecture (driven by latency, bandwidth, and fault tolerance); MIPI Alliance Physical AI BoF chair Edo Cohen added the division of responsibilities between local real-time inference in the hand (millisecond-level grip force adjustment) and central task planning, but also noted that centralized architectures may be better on BOM, power, and software complexity. TI advocates a “dumb sensors + central fusion” route to save power. The common point: safety must never be left solely to AI models; independently certified hardware components must provide the backstop;
  • Escalated security threat model: the CTO of Secure-IC (under Cadence, an important supplier of RISC-V security IP) pointed out the essential difference between humanoid robots and autonomous driving — physical proximity (homes, hospitals, schools) — making man-in-the-middle attacks and LLM manipulation of vulnerable groups realistic risks; the convergence of functional safety and cybersecurity becomes a hard requirement;
  • RISC-V angle: remarks by James Prior, marketing lead at MIPS (under GF, now fully pivoted to RISC-V), were quoted separately — “customers are not asking when to adopt RISC-V, but how to move to RISC-V (whom to partner with, what path to take),” and he emphasized that the robotics industry (kindred to automotive/industrial) is risk-averse and needs a supply narrative of “software first, open standards, ecosystem vitality.” This corroborates yesterday’s MIPS three-platform (Acies/Actus/Aegis) launch and Jon Peddie Research’s 09-04 follow-up analysis (“MIPS gives physical AI three ways to think”): competition in RISC-V for embodied intelligence is shifting from “chip specs” to “architectural voice + security certification + ecosystem services.”

V. Summary and Trend Observations

  1. Toolchain and standards converge on “serverization” along two lines: GCC 17 adds RISC-V native -mcpu/-mtune=native (Kito Cheng/SiFive), and SiFive systematically laid out the RVA/RVB profiles, security, and matrix extension roadmap at Hot Chips — compilation, profiles, and OS layers are all preparing for the first RVA23 server silicon (shipping this year); this week’s two RISC-V talk reports from Hot Chips (the NVIDIA CUDA requirements list reported 09-02, and the SiFive standards evolution added today) are now complete.
  2. CUDA-on-RISC-V cadence clarified: third-party media (igor’sLAB) and the RISC-V International weekly both confirm BigSky’s positioning as a “porting validation platform” and the fact of a RISC-V host + Blackwell GPU demonstration; NVLink Fusion custom chips no earlier than 2027 — the judgment that the software stack leads and silicon follows is unchanged, and RISC-V server shipments should not be overestimated in the near term.
  3. On the domestic open-source side, only the XiangShan family is active: Kunminghu main repo vector/floating-point refactoring (VCVT, VIMac, LoadQueueReplay) advances in parallel with synchronized fixes in the AI fork XSAI, with a complete development loop; T-Head/Nuclei/Sophgo/SpacemiT and others remain in the post-release quiet period.
  4. Watch Yizhuang for ecosystem moves: the HICOOL RISC-V+AI Challenge concluded (first prize: RISC-V+OpenHarmony NVR edge AI), jointly organized by ESWIN Computing and the Beijing RISC-V Digital Infrastructure Innovation Center, with ACT opened free of charge — the “industrial belt incubation” model for domestic RISC-V+AI is taking shape.
  5. Limitations note: there were no major new-product-launch-level events today, making it a “light day” dominated by standards/toolchain/ecosystem conference information; the BigSky and MIPS-related reports are media echoes of already-reported main events, covered here only as trend items without repetition; Google News Chinese sources returned zero hits for domestic teams, so the domestic section relies on GitHub commit checks and official Yizhuang channels.

Appendix: Complete Source List

Source Check Result
fetch_news.py candidates (10 items) Included: Phoronix GCC 17 (1.1), STH Hot Chips SiFive talk (1.2; 2 other STH clickbait headlines from the same source excluded), SemiEngineering humanoid compute (4.1), igor’sLAB BigSky (2.1 trend), JPR MIPS analysis (4.1 narrative); Excluded: TickrCast (ESP32-S3 is Xtensa, not RISC-V), ESP32-P4 weather station (geek DIY, low value), RISCV-Embedded teaching repo (30 stars, low value)
gnews “RISC-V” when:1d (English) Mostly overlapping with the candidate list (GCC 17, JPR, STH, igor’sLAB); SEALSQ wolfTPM (post-quantum TPM, weak RISC-V relevance, excluded), NextSilicon personnel, Amlogic A311Y3 SOM (all non-RISC-V noise, excluded)
gnews SiFive when:3d / igor’sLAB BigSky follow-up interpretation (included as 2.1 trend item); no new product events in the window
gnews Chinese team queries when:3d (T-Head/XuanTie/Sophgo/SpacemiT/XiangShan, etc.) Mostly noise (XiangShan = Beijing Xiangshan Park / Xiangshan Co. M&A stock news, Sophgo = computing-power coordination), zero valid hits; “RISC-V chip when:3d” hit the HICOOL conclusion (included 3.2), Lingrui Zhixin old news reposted (reported 09-02, excluded), Electronic Engineering Album review (outside window, excluded)
HN Only 1 item: STH Hot Chips SiFive talk transcript (included 1.2)
GitHub org scan (9 teams) XiangShan active in 13 repos (6 commits in main repo, see 3.1/3.3); Nuclei/SpacemiT/Sophgo/Sipeed each 1-2 routine maintenance; T-Head/StarFive/RevyOS/ESWIN 0
GitHub topic:risc-v active projects Routine pushes (cva6, tock, riscv-unified-db, arduino-pico, etc.), no major releases in the window