RISC-V Daily Intelligence Report (2026-09-01)
Research window: Past 24 hours (2026-08-31 08:18 ~ 2026-09-01 08:18, Beijing Time) Sources: HN, Google News aggregation, CNX Software, Hackster.io, Python Insider, ACCESS Newswire/PR-Inside, Demócrata, OSChina, GitHub API (org/repo commit search), etc. (see appendix for details)
In This Issue
- I. Open Source Community and Software Ecosystem
- CPython Officially Supports RISC-V (Tier 3 Platform): A Software Ecosystem Milestone (08-24 announcement / 08-31 coverage)
- Arduboy CHGame Rev0: $39 Open Source RISC-V Color Handheld (08-31)
- II. Product and Ecosystem Updates
- Micro Magic MagicV Processor Announced for Immediate Availability, Claimed World’s Fastest/Lowest-Power 64-bit RISC-V (08-31)
- Spain’s Indra-UPM Delivers First Batch of Four Chip Tape-outs, Including a RISC-V Architecture Chip (08-31)
- III. Domestic Team Updates and Deep Dives
- Domestic Team GitHub Activity: RevyOS Adds K1/K3 Kernel Configs, Sophgo sophon-tools Release Batch Lands (08-31)
- IV. Embodied Intelligence and Robotics Special Section
- MicroDuck: Hugging Face and Pollen Robotics’ Open Source Bipedal Robot (Ecosystem Reference, Main Controller Is Not RISC-V) (08-27/31)
- V. Summary and Trend Observations
- Appendix: Complete Source List
I. Open-Source Community and Software Ecosystem
1.1 CPython Officially Supports RISC-V (Tier 3 Platform): A Software Ecosystem Milestone
Date: 2026-08-24 (Python Insider announcement) / 08-31 (Adafruit repost, HN hot thread) Source: Python Insider (official announcement), RISE Project blog, Adafruit report (gnews link)
CPython maintainer Stan Ulbrych announced on the official Python Insider blog that RISC-V has officially become a Tier 3 supported platform for CPython (PEP 11). The key requirement for this milestone was continuous testing on real hardware — the RISE Project provided multiple physical RISC-V machines for CPython buildbot and architecture-related issue debugging; other major contributors include RISE’s Ludovic Henry, Furkan Onder, and Emma Smith, while Ulbrych’s own work was funded by a Sovereign Tech Agency fellowship. Next steps: use the RISE RISC-V Runners program to plug RISC-V directly into CPython’s official CI (enabling feedback before merge), and pursue an upgrade to Tier 2 in the long term; meanwhile, explore architecture-level performance optimizations that leverage RISC-V features. The announcement also calls on the community to build on real RISC-V hardware and report issues. Published 08-24, this announcement was not covered in yesterday’s report and is included here as a catch-up; the 08-31 Adafruit repost and Hacker News hot thread gave it high visibility within the window, making it the most important RISC-V software ecosystem milestone of the past week.
1.2 Arduboy CHGame Rev0: A $39 Open-Source RISC-V Color Handheld
Date: 2026-08-31 Source: Hackster.io, Arduboy store
The classic open-source handheld Arduboy has launched a new platform, the CHGame Rev0: a $39 bare-board development kit whose main controller is the WCH CH32X035G8U6 — a 32-bit RISC-V microcontroller at 48 MHz with 64 KB Flash, 20 KB RAM, DMA, and programmable I/O (PIO); it comes with a 1.44-inch ST7735 color LCD (128x128, 16-bit color), eight buttons, a piezo speaker, a microSD slot, and a 200 mAh battery. It is Arduino-compatible with no driver needed, and the board’s silkscreen labels GPIO/function zones and exposes GPIO, I2C, and UART expansion ports; the official positioning is “a RISC-V development board with a built-in screen and buttons.” It is currently an early kit funding development, with mass-production costs expected to fall further. This marks a typical landing of a domestic RISC-V MCU (WCH) in the overseas open-source hardware community, extending the popularity of the CH32V003 family’s “dirt-cheap RISC-V handheld” trend.
II. Product and Ecosystem Updates
2.1 Micro Magic MagicV Processor Announced for Immediate Availability, Claimed World’s Fastest/Lowest-Power 64-bit RISC-V
Date: 2026-08-31 Source: PR-Inside (ACCESS Newswire release), Middletown Life reprint
US Silicon Valley private company Micro Magic announced that its MagicV processor family is available immediately, offering 1/2/4-core configurations, with a live demonstration of multi-core MagicV running Linux, Zephyr, and FreeRTOS. The release reiterates figures claimed over the years: 5 GHz at 1.1V single-core, 13,000 CoreMarks; 4.25 GHz at 0.8V drawing only 200 mW (11,000 CoreMarks); energy efficiency of 110,000 CoreMarks/Watt; ultra-low-power core at 1 GHz drawing only 10 mW; data based on a 16nm process, with more advanced nodes available. CEO Mark Santoro said customers were impressed by the performance and “stunned” by the low power. Note: all performance numbers are vendor claims, with no third-party benchmarks or public tape-out evidence; the company has long sought strategic partnerships or acquisition, so this should be tracked as a “claim pending verification” item (Micro Magic has issued similar claims since 2021; this is the first time it has announced purchasable availability).
2.2 Spain’s Indra-UPM Delivers First Four-Chip Tape-Out, Including a RISC-V Architecture Chip
Date: 2026-08-31 Source: Demócrata
The joint chair “Microelectronics That Changes the Future” of Spain’s Indra Group and the Universidad Politécnica de Madrid (UPM) has completed the design of its first four chips and sent them for manufacturing; they have now been produced and delivered, entering the evaluation and characterization phase. Specifically, three 65nm silicon chips (taped out at TSMC) and one indium phosphide (InP) photonic integrated chip (researching beamforming architectures). One of the silicon chips uses the RISC-V architecture, while the other two are used for 3D heterogeneous integration testing, with the goal of advancing RF module miniaturization and integration density. The project operates in a pre-competitive environment with student and industrial PhD participation, serving Europe’s technology sovereignty strategy; Indra is also the largest shareholder of Sparc Foundry, which focuses on III-V photonics manufacturing (its Vigo fab is expected to start production in 2027). This move is in step with arrangements such as Spain’s OpenChip (a RISC-V International board member), representing a mid-sized landing of the European sovereign chip route on the RISC-V side.
III. Domestic Team Updates and Deep Dive
3.1 Domestic Team GitHub Activity: RevyOS Adds K1/K3 Kernel Configs, Sophgo sophon-tools Release Batch Lands
Date: 2026-08-31 Source: revyos/linux commits, sophgo/sophon-tools commits, sophgo/mcu PR#84, spacemit-com/docs-buildroot, sipeed/maix_ax620e_sdk
Seven domestic team GitHub organizations were checked during the window: T-Head (XUANTIE-RV), Nuclei (Nuclei-Software), ESWIN Computing (eswincomputing), and Espressif (espressif) had no relevant pushes, continuing the post-release quiet period. Three had substantive activity:
SpacemiT ecosystem RevyOS (revyos/linux, batch commits by Han Gao on 08-31) is the most notable item: new spacemit K1/K3 kernel config files, linuxboot boot configuration, enabling CONFIG_ERRATA_PICOHEART and Banana Pi F3 (K1) USB2 support, plus enabling K3 platform DC (display controller) and UFS support, while also converting TH1520 USB-related options to modules and adjusting serial port count configuration. This is a batch of kernel configuration enhancements for the RevyOS distribution targeting both K1/K3 platforms, indicating the SpacemiT ecosystem is laying the software groundwork for the K3 new platform’s display/storage capabilities. spacemit-com/docs-buildroot removed the K1 secure boot documentation section the same day (documentation cleanup).
Sophgo: sophon-tools had 15 commits on 08-31 (zetao.zhang), a pre-release batch for v26.08.31 — fixing BMSSM (board management system) OTA upgrade/rollback where the first workflow was mistakenly killed by its own handler lock (MYS-451 race condition), changing sophliteos upgrade semantics to system-level with a secondary confirmation code, and completing deb packaging control members and empty preinst (to root-cause the dpkg obsolete-info error under overlayfs), among others — all system management stack stability hardening; sophgo/mcu concurrently fixed the SM5MINI(v20) i2c_slave_reset erroneously clearing IP information issue.
Sipeed: maix_ax620e_sdk fixed a UVC endpoint lifecycle issue (camera stream stability), minor maintenance.
Overall, domestic teams remain in a regular iteration phase with no architecture-level/product-level releases; K3 platform software stack progress is the most noteworthy signal to track within the window.
IV. Embodied Intelligence and Robotics Special Chapter
4.1 MicroDuck: Hugging Face and Pollen Robotics’ Open-Source Bipedal Robot (Ecosystem Reference, Main Controller Not RISC-V)
Date: 2026-08-27 (release) / 08-31 (OSChina report) Source: OSChina, Pollen Robotics official site, Interesting Engineering
The Hugging Face robotics team (France’s Pollen Robotics, merged in 2025-04) launched MicroDuck: a 25 cm, under-800 g open-source bipedal robot with 15 motors, camera, depth sensor, dual IMU, and a grippable beak, at $399 for pre-order (opened 08-27), capable of walking, squatting, getting up after falls, and even roller-skating; the full software stack is open source (Microduck and Microduck RL repositories), covering control, simulation, reinforcement learning, and sim-to-real, and supports “playing” to train new skills with a game controller. Pre-order sales exceeded $2.5 million on the first day, with a peak of one unit sold every 4 seconds, targeting delivery before Christmas 2026. RISC-V relevance: the main controller is Rockchip RK3566 (ARM platform), not RISC-V hardware; included as an open-source embodied intelligence ecosystem reference — its “open-source hardware + open-source RL software stack + low-price proliferation” model is isomorphic to the RISC-V robotics ecosystem path, and the portability of its software stack (50 Hz control loop, policy deployment, OTA update mechanism) is worth learning from for RISC-V platforms; it also provides a market validation sample for “open-source hardware moving toward consumer-grade embodied intelligence.”
V. Summary and Trend Observations
- Software ecosystem milestone: CPython lists RISC-V as a Tier 3 supported platform (PEP 11), with the RISE Project providing real-hardware buildbot as the key to achieving this; the next step is integration into official CI and pushing for Tier 2. Python is the primary language for AI and scientific computing, and this event has significant long-term value for the RISC-V developer ecosystem.
- Open-source hardware continues to democratize: Arduboy CHGame Rev0 brings the WCH CH32X035 RISC-V handheld to the mainstream open-source hardware community at $39, adding another example of domestic RISC-V MCU overseas penetration.
- High-end claims and sovereign chips in parallel: Micro Magic announced MagicV is available for purchase (all performance figures are vendor claims, pending verification); Spain’s Indra-UPM four-chip tapeout includes a RISC-V design, extending Europe’s sovereign chip path into RF/photonics directions.
- Domestic teams enter a regular iteration phase: seven organizations had no release-level activity; RevyOS adding K1/K3 kernel configs (including linuxboot, K3 DC/UFS) is the most substantive progress in the window, while Sophgo’s sophon-tools v26.08.31 release batch focuses on system stack stability hardening.
- Embodied intelligence ecosystem reference: MicroDuck’s $2.5 million first-day pre-orders validate strong demand for “low-cost open-source robots + RL software stack,” but its main controller is ARM; the opportunity window on the RISC-V side remains in the September domestic robotics expo season and various vendors’ SoC robotics SKUs.
- Limitations note: Google News Chinese sources remain limited for direct coverage of domestic teams (noise pollution from same-name entities), and domestic coverage partly relies on GitHub commit verification; Micro Magic metrics have not been independently verified; some information in the MicroDuck and Indra items comes from vendor/academic press releases and has been cross-checked as much as possible.
Appendix: Complete Source List
| No. | Event | Source Links |
|---|---|---|
| 1 | CPython supports RISC-V (Tier 3) | Python Insider, RISE Project, Adafruit (gnews) |
| 2 | Arduboy CHGame Rev0 | Hackster.io, Arduboy |
| 3 | Micro Magic MagicV | PR-Inside, Middletown Life |
| 4 | Indra-UPM four chips | Demócrata |
| 5 | RevyOS K1/K3 kernel configuration | revyos/linux |
| 6 | Sophgo sophon-tools release | sophgo/sophon-tools, sophgo/mcu |
| 7 | Sipeed maix_ax620e_sdk | sipeed/maix_ax620e_sdk |
| 8 | MicroDuck robot | OSChina, Pollen Robotics, Interesting Engineering |
| 9 | Candidate list | candidates.txt (fetch_news.py output + gnews supplementary search + GitHub API verification) |