Research window: Past 24 hours (2026-08-30 08:18 ~ 2026-08-31 08:18, Beijing Time) Sources: HN, Google News aggregation, CNX Software, Phoronix, 9to5Linux, eeNews Europe, HPCwire, ServeTheHome, SDxCentral, ITHome/Sina Tech, CSDN, GitHub API (org/repo commit search), etc. (see appendix)

In This Issue

  • I. Open Source Community & Software Ecosystem
    • Linux 7.3-rc1 released: RISC-V interrupt controller code refactored into the generic ACPI IRQ framework (08-31)
    • openKylin 3.0 officially released: single source for four architectures, broadest RISC-V support, RVA23 and RVV optimizations (08-28/29)
    • Two open source projects: ClickDOOM emulates RISC-V via ClickHouse SQL to run 1993 DOOM; LabWired Core deterministic firmware simulator (08-31)
  • II. Product & Ecosystem Developments
    • XCENA MX1: Hot Chips 2026 deep dive into a CXL compute-storage device with thousands of RISC-V cores (08-26/28)
    • India’s Aheesa Vihaan first silicon brings up: 64-bit RISC-V networking SoC passes first round of hardware validation (08-30)
    • Radxa Linkr ecosystem reference: USB-stick-sized IP KVM with a RISC-V coprocessor in the main controller (08-30)
  • III. Domestic Team Developments & Deep Dive
    • GitHub activity check on domestic teams: overall quiet within the window, only minor iterations from Sophgo/SpacemiT (08-30/31)
  • IV. Embodied Intelligence & Robotics Special Section
    • No new RISC-V embodied intelligence hardware within the window; on the software side, openKylin 3.0 completes adaptation for humanoid robots and more (trend continues)
  • V. Summary & Trend Observations
  • Appendix: Complete Source List

I. Open-Source Community and Software Ecosystem

1.1 Linux 7.3-rc1 Released: RISC-V Interrupt Controller Code Refactored into Generic ACPI IRQ Framework

Date: 2026-08-31　Source: 9to5Linux, LKML (Linus’s release email), Phoronix: Linux 7.3 adds several new RISC-V extensions, Phoronix: KVM Chainsaw cleanup merged

Linus Torvalds released the first release candidate of Linux 7.3, 7.3-rc1, on 08-30 (early 08-31 Beijing time), formally closing the two-week merge window. Linus said this rc1 ranks among the largest by commit count, driven mainly by a bulk update of AMD DCN6 register headers. Changes directly relevant to RISC-V: the irqchip/ACPI code refactor extracts the generic portion of RISC-V interrupt controller management code and merges it into the common ACPI IRQ code, to support the ACPI probe ordering for ARM-side GICv5 IWB (the refactor also paves the way for subsequent RISC-V ACPI interrupt support); support for several newer RISC-V extensions was merged during the merge window (reported by Phoronix on 08-24). On the KVM side, this cycle was mainly fixes and cleanups: “KVM Chainsaw” (splitting the giant kvm_mmu data structure) landed, AMD SEV/SEV-ES ENCRYPT/DECRYPT were changed to full-page allocation to fix data corruption caused by PSP firmware page assignment, and the SEV-SNP population ioctl was hardened. Following the weekly Sunday rc cadence, the final Linux 7.3 release is expected on October 18 or 25. This item is the most important kernel-side event in the window.

1.2 openKylin 3.0 Officially Released: Four Architectures from a Single Source, Broadest RISC-V Adaptation, RVA23 and RVV Optimization Support

Date: 2026-08-28/29　Source: CSDN/OpenAtom, ifeng Tech, Sina Tech/ITHome

OpenAtom’s openKylin 3.0 was officially released on 08-28. The kernel jumped a generation from Linux 6.6 to 7.0, with more than 180 core components iterated in sync, including GCC 15, glibc 2.42, LLVM 22, and JDK 25. The three points most relevant to the RISC-V ecosystem: (1) Single-source support for four major architectures—x86, ARM, RISC-V, and LoongArch; the project calls openKylin “one of the operating systems with the broadest RISC-V adaptation and highest maturity,” now supporting the latest RVA23 standard, with per-architecture hardware compatibility lists published on Gitee; (2) AI inference on the RISC-V platform is optimized via RVV instructions, delivering 2x to 5x speedups in FP32 scenarios and up to 36.5x in FP16 scenarios; (3) Scenario coverage extends to embodied-intelligence adaptation such as the “Linglong” humanoid robot, AI unmanned vehicles, and AI robotic arms, as well as multi-architecture industrial hardware platforms. On security, it integrates NIST’s three post-quantum cryptography standards (ML-KEM/ML-DSA/SLH-DSA) with system-level invocation via openHiTLS, and supports Rust For Linux kernel driver development. On the agent side, it builds an open foundation: mainstream agents such as KylinBot and OpenClaw directly invoke desktop capabilities via the MCP protocol. As a key link in the domestic OS segment of the RISC-V software ecosystem, openKylin 3.0’s RVA23/RVV adaptation progress is worth continued tracking.

1.3 Two Open-Source Projects: ClickDOOM Simulates RISC-V to Run 1993 DOOM Using ClickHouse SQL; LabWired Core Deterministic Firmware Simulator

Date: 2026-08-31　Source: MarcusKainth/ClickDOOM, w1ne/labwired-core

Two newly active open-source projects (spotted via the GitHub API within the window): ClickDOOM compiles the C source of id Software’s 1993 DOOM engine as-is into a bare-metal RV32IM binary via the doomgeneric porting layer, then runs it instruction by instruction on a “RISC-V CPU emulator implemented entirely in ClickHouse SQL” (fetch/decode/execute, registers, RAM, and MMIO all inside SQL); frame 220 of demo3 matches the reference emulator’s output hash after 220 million instructions, validating emulation correctness. Its predecessor was Click-V (a RISC-V CPU in SQL); dual-licensed Apache-2.0/GPL-2.0, it is a fun hardcore project that turns serious ISA emulation into an SQL extreme challenge. LabWired Core is a firmware simulator written in Rust: after loading a firmware ELF, it executes deterministically on a modeled chip (CPU, bus, peripherals, sensors), and the same ELF plus board manifest produces identical traces on any machine, making it usable as a CI gate (pass/fail exit codes); it supports ARM Cortex-M and RISC-V, with 61 stars. Together, the two reflect the vitality of the RISC-V toolchain/emulation ecosystem in the “simulation-as-testing” direction.

II. Product and Ecosystem Developments

2.1 XCENA MX1: Hot Chips 2026 Details a CXL Computational Memory Device with Thousands of RISC-V Cores

Date: 2026-08-26 (Hot Chips talk) / 08-28 (coverage)　Source: HPCwire, ServeTheHome, StorageNewsletter

At the Hot Chips 2026 Memory session (08-26, joint talk with Samsung), XCENA detailed the architecture and measured performance of its CXL Type 3 computational memory device MX1: 3,072 custom 1.4GHz RISC-V cores form a Memory Acceleration Unit that executes memory-intensive workloads in place; four DDR5-8400 channels scale to up to 2TB of memory, with SSDs presented as byte-addressable CXL memory via the root port; an integrated vector engine delivers roughly 3 TFLOPS of FP32/FP16 dot-product throughput (targeting vector search and KV-cache scoring). Developers program in standard C/C++ or Rust, dispatching across thousands of cores via an LLVM toolchain + PXL runtime (shared virtual address space). Measured against host CPU access over CXL: a single MX1 delivers up to 4.7x throughput and 18.7x energy efficiency; against local DDR5: 2.0x throughput and 6.2x energy efficiency. The device represents the “large-scale RISC-V near-memory computing + CXL memory pooling” route, paired with Samsung’s rack-level CXL memory offerings, and is worth watching for its real impact on the AI memory wall narrative.

2.2 India’s Aheesa Vihaan Lights Up on First-Pass Silicon: 64-bit RISC-V Networking SoC Passes First Round of Hardware Validation

Date: 2026-08-30　Source: SDxCentral, The Hans India, Aheesa official site

Chennai-based startup Aheesa Digital Innovations announced that its Vihaan series achieved successful first-pass silicon, with first-round hardware validation confirming performance targets. Vihaan is a 64-bit RISC-V-driven networking SoC aimed at broadband access scenarios: high-performance routers, managed switches, and unified threat management (UTM) appliances; an edge variant targets IoT gateways and industrial automation (local low-latency processing). Founded in 2021, the company’s executives come from Wipro, Microchip, and AMI, and CEO Sridharan Mani previously served as a senior software development manager at Amazon; it is funded by India’s Ministry of Electronics and Information Technology (MeitY) Design Linked Incentive (DLI) scheme, with roughly US$4.19 million raised (including the Tamil Nadu Infrastructure Fund TNIFMC). Timeline: first tapeout in January 2026, with production tapeout targeted for 2027. A MeitY statement said its progress “shows that India’s semiconductor design is moving out of the lab.” This marks a landmark advance for India’s RISC-V sovereign chip route (following the IIT Madras-affiliated Shakti) in the commercial networking silicon direction.

2.3 Radxa Linkr Ecosystem Reference: A USB Drive-Sized IP KVM Whose Main Controller Includes a RISC-V Coprocessor

Date: 2026-08-30　Source: CNX Software, Radxa product page

CNX Software teardown review of Radxa’s new Linkr: a USB drive-sized IP KVM (70x22x12mm) that captures the target machine’s display over HDMI + emulates keyboard and mouse over USB, supports USB-C direct connection, Ethernet, and Wi-Fi 6 (AIC8800) for remote control, operates entirely in a browser with no app install, and supports Tailscale VPN, two-factor authentication, and takeover by AI agents such as OpenClaw/Hermes. The main controller is Rockchip RV1106G3 (Arm Cortex-A7 @1.2GHz + integrated RISC-V coprocessor), with a 1 TOPS NPU, 256MB of on-chip memory + optional 16GB eMMC. The RISC-V connection: the RV1106 embeds a RISC-V coprocessor (also used by the similar JetKVM), and Radxa itself is a leading RISC-V single-board vendor; however, Linkr’s main compute side remains Arm, making this an ecosystem reference entry rather than a native RISC-V product. Priced from US$59, currently out of stock across four channels.

III. Domestic Team Developments and Deep Dive

3.1 GitHub Activity Check on Domestic Teams: Overall Quiet in the Window, Only Minor Iterations from Sophgo/SpacemiT

Date: 2026-08-30/31　Source: sophgo/sophon-tools, spacemit-com/openocd, GitHub orgs API (XUANTIE-RV/sophgo/Nuclei-Software/spacemit-com/eswincomputing/revyos/sipeed)

A window check of GitHub organization activity across seven domestic teams (orgs repos API pushed_at filtering): T-Head (XUANTIE-RV, 72 repos), Nuclei (Nuclei-Software, 42 repos), ESWIN Computing (eswincomputing, 16 repos), and Sipeed (sipeed) had no pushes in the window, all in a post-release quiet period; Sophgo (sophgo) had only one push to sophon-tools (on the morning of 08-30, i.e., the merge of the pre-release security hardening batch reported yesterday); SpacemiT (spacemit-com) had two pushes, to docs-chip (the P3 PMIC documentation reported yesterday) and to the openocd repo (a read-only upstream mirror sync, no independent development); the seven pushes across Revyos org repos were all SG204x firmware chain syncs (fsbl.bin/EDK2 cross-compiler, reported yesterday). Conclusion: there were no architecture-level or product-level new developments from domestic teams in the window, consistent with the typical quiet period after a major release; the next window to watch is each team’s September release cadence (Sophgo CV84X mass-production support, Nuclei’s first moves after listing, and follow-ups to XiangShan KunminghuV2).

IV. Embodied Intelligence and Robotics Special Section

4.1 No New RISC-V Embodied Intelligence Hardware in the Window; on the Software Side, openKylin 3.0 Completes Adaptation for Humanoid Robots and More

Date: 2026-08-31　Source: Compilation of items in this issue (see appendix for details)

No new RISC-V embodied intelligence hardware releases were found in this window, and the landscape continues the assessment of the past week: RISC-V progress on the embodied intelligence side is concentrated at the software and platform adaptation layer. The most relevant signal this issue comes from openKylin 3.0 (see 1.2): its scenario coverage explicitly includes adaptation for the “Linglong” humanoid robot, AI unmanned vehicles, AI robotic arms, and other embodied intelligence use cases, and supports RISC-V and other multi-architecture industrial hardware platforms — that is, the domestic OS camp is bringing RISC-V embodied intelligence into its default adaptation matrix; meanwhile, RVV-optimized AI inference performance on RISC-V (up to 36.5x speedup in FP16) provides measured evidence for on-device model deployment. In addition, an eeNews Europe technology overview (08-25, ecosystem reference) noted that Europe’s EPAC 1.0 accelerator achieves 12 TOPS/W with a RISC-V control core + domain-specific AI tiles, confirming the applicability of an open ISA under the power constraints of robotics and autonomous systems. For new hardware, the window to watch is September’s domestic robotics trade show season and each vendor’s robot SKU release cadence for their SoCs.

V. Summary and Trend Observations

  1. Kernel mainline advances: Linux 7.3-rc1 released, with multiple new RISC-V extensions merged during the merge window; RISC-V interrupt controller code was refactored into the generic ACPI IRQ framework, paving the way for RISC-V ACPI interrupt support; on the KVM side, the focus was SEV fixes and the splitting of kvm_mmu mega-structures.
  2. Accelerating RISC-V adaptation in domestic OSes: openKylin 3.0 released from the same source across four architectures, self-assessed as having “the broadest RISC-V adaptation and the highest maturity,” with RVA23 support + RVV inference optimization (up to 36.5x in FP16) + embodied intelligence scenario coverage, steadily raising software stack readiness.
  3. RISC-V pushing deeper into the data center: XCENA MX1 attacks the AI memory wall with 3,072-core RISC-V near-memory computing + CXL 3.2 pooling, with measured throughput/energy efficiency far ahead of host CPUs (up to 4.7x/18.7x), complementing SiFive’s BigSky server delivery (reported 08-29).
  4. Global sovereign chip routes blossoming in multiple places: India’s Aheesa Vihaan (funded by the DLI scheme) lit up on first-pass silicon, making a move in commercial networking silicon after Shakti, with a clear 2027 production tapeout target.
  5. Domestic teams entering a post-release quiet period: the seven major organizations showed no architecture-level activity on GitHub in the window, a normal cadence after major releases; the next point to watch is each vendor’s September release window.
  6. Limitations note: Google News Chinese-language sources provide limited direct coverage of domestic teams (terms such as T-Head/XiangShan are polluted by same-name noise), so the domestic section relies on GitHub commit checks; Radxa Linkr’s main controller is Arm + a RISC-V coprocessor and is included as an ecosystem reference; gnews redirect pages cannot be read directly, so all body text is based on the original sites.

Appendix: Complete Source List

No. Event Source Link
1 Linux 7.3-rc1 released 9to5Linux, LKML
2 Linux 7.3 adds RISC-V extensions Phoronix
3 KVM Chainsaw merged Phoronix
4 openKylin 3.0 released CSDN, Phoenix Net, Sina/ITHome
5 ClickDOOM GitHub
6 LabWired Core GitHub
7 XCENA MX1 @ Hot Chips 2026 HPCwire, ServeTheHome, StorageNewsletter
8 Aheesa Vihaan first tapeout SDxCentral, Aheesa, Design&Reuse (February tapeout background)
9 Radxa Linkr CNX Software, Radxa
10 GitHub verification of domestic teams sophgo, spacemit-com, XUANTIE-RV, Nuclei-Software, eswincomputing, revyos, sipeed
11 eeNews technology overview (ecosystem reference) eeNews Europe
12 Candidate list candidates.txt (fetch_news.py output + gnews supplementary search)