Research window: Past 24 hours (2026-08-24 08:18 ~ 2026-08-25 08:18 Beijing time) Sources: HN (Algolia API), Google News RSS aggregation (English + Chinese, via proxy), direct scraping of Phoronix / Chips and Cheese / HotHardware / SiFive official sites, GitHub API (commit searches across XiangShan/SpacemiT/T-Head/Nuclei/ESWIN/StarFive/Espressif organizations; see appendix)

Today’s Index

  • I. Open-Source Community and Software Ecosystem
    • CPython Officially Supports RISC-V: Becomes an Official Tier 3 Platform (08-25)
    • Linux 7.3 Adds Support for Multiple New RISC-V Extensions (08-24)
    • Hot Chips 2026: NVIDIA Details Technical Requirements for Porting CUDA to RISC-V (08-24)
    • RISC-V Instruction Set Manual Enters ISO/IEC DIS 26791-1 International Standard Draft Stage (08-24)
  • II. Product and Ecosystem Developments
    • SiFive BigSky SF-2U870: World’s First Rack-Mount 2U RISC-V Enterprise Server Launched (08-24)
    • IAR and Neusoft Reach Form Strategic Partnership: Filling the Gap in RISC-V Automotive-Grade Toolchains (08-24/25 reports)
    • Andes D23-SE Receives ISO 26262 ASIL-B/ASIL-D Functional Safety Certification (08-24 reports)
    • LilyGo T-Display K230 Kit: Tech Times Reports Current Ubuntu Cannot Run on It (08-24/25)
  • III. Domestic Team Updates and Deep Dives
    • XiangShan: COVE/MPT Fixes Continue to Converge, Multi-Track Progress in Performance and Memory Subsystems (08-24~25)
    • SpacemiT: New Video Decoding API and Developer Tool Documentation Updates (08-24)
    • ESWIN Computing: Hong Kong IPO Disclosure Reveals Cumulative Losses Exceeding RMB 5.2 Billion (08-25)
    • T-Head/Nuclei/StarFive Routine Observations + HICOOL RISC-V+AI Challenge Semifinals (08-24)
  • IV. Focus Chapter: Embodied Intelligence and Robotics
    • No New Dedicated News: Continued Observation of Edge Computing and Robotics Scenarios (08-24)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List and Supplementary Query Checklist

I. Open Source Community and Software Ecosystem

1.1 CPython Officially Supports RISC-V: Becomes an Official Tier 3 Platform (08-25)

Date: 2026-08-25 (same period as blog publication; HN submission 08-24 20:12 UTC = 08-25 04:12 Beijing)　Source: blog.python.org, HN

CPython has officially announced RISC-V as an officially supported platform, listed as tier 3 under PEP 11. Supporting path: the RISE Project provided multiple real RISC-V hardware units as buildbot testing and architecture issue debugging environments (community contributors including Ludovic Henry, Furkan Onder, Emma Smith), and a Sovereign Tech Agency fellowship funded this round of architecture support work. Next steps: leverage RISE RISC-V Runners to connect RISC-V directly to CPython’s official CI (faster feedback than buildbot), and in the long term push for upgrading to tier 2 and pursue architecture-specific performance optimizations. Significance: Python is the backbone language of the AI/robotics software stack, and official tier 3 support fills in a critical piece for software availability in RISC-V edge and server scenarios (cf. the server progress in 2.1).

1.2 Linux 7.3 Adds Support for Multiple New RISC-V Extensions (08-24)

Date: 2026-08-24 (Phoronix 10:12 UTC = 18:12 Beijing)　Source: Phoronix

The in-development Linux 7.3 has merged discovery and enumeration support for several newer RISC-V ISA extensions: indirect CSR access (Smcsrind/Sscsrind), counter privilege filtering (Smcntrpmf), S-mode counter configuration (Ssccfg), counter delegation (Smcdeleg, covering all privilege levels), memory atomicity/consistency class (Zicclsm unaligned memory access, Ziccamoa atomic operations, Ziccif instruction fetch atomicity, Ziccrse LR/SC forward progress, Za64rs reservation set), and QoS identifiers (Ssqosid, memory/cache bandwidth monitoring). There are also CFI Shadow Stack handling improvements, QoS tag context switching, and UEFI Runtime services for reboot/shutdown. This batch of extensions is primarily server- and performance-monitoring-oriented, directly echoing the feature push for RVA23 server platforms (see 2.1).

1.3 Hot Chips 2026: NVIDIA Details Technical Requirements for Porting CUDA to RISC-V (08-24)

Date: 2026-08-24 (published by Chips and Cheese; HN 68 points, 9 comments)　Source: Chips and Cheese, HN

At Hot Chips 2026, an NVIDIA talk introduced extending CUDA support to RISC-V: it requires the RVA23 profile and the RISC-V server SoC / server platform specifications (including baseline features such as RAS and a dedicated security processor); additional requirements include PCIe coherency (otherwise software must explicitly invalidate between DMA and CPU caches, which the CUDA stack struggles to handle), inter-device P2P PCIe, and vector extension predicate support, to avoid a “lowest common denominator” that precludes the use of performance-enhancing instructions; the ACPI issue previously hindered porting and has been resolved by the 2025 UEFI Forum’s RISC-V ACPI support and last year’s ratified BRS (Boot and Runtime Services) specification. South Korean media outlet Maeil Business Newspaper (Korea) concurrently reported that NVIDIA plans to extend AI server CPU support from Arm/x86 to RISC-V. Combined with SiFive’s confirmation that CUDA already runs in practice on its BigSky platform (see 2.1), “CUDA on RISC-V” has moved from a 2025 statement into the stage of technical requirements being implemented.

1.4 RISC-V Instruction Set Manual Enters ISO/IEC DIS 26791-1 International Standard Draft Stage (08-24)

Date: 2026-08-24 (HN 12:54 UTC = 20:54 Beijing)　Source: HN, iso.org/standard/94578

The RISC-V instruction set manual has entered the International Standard Draft (DIS) stage under the designation ISO/IEC DIS 26791-1—in the ISO/IEC JTC 1 standards process, DIS is put to member body vote and is a key milestone toward formal international standardization. As a landmark move for an open ISA toward ISO standards, it is consistent with RISC-V International’s standardization push within JTC 1. Note: the ISO website page is anti-scraping and its body text cannot be directly retrieved; the technical scope is subject to the official website and the DIS text.

II. Product and Ecosystem Updates

2.1 SiFive BigSky SF-2U870: World’s First Rack-Mountable 2U RISC-V Enterprise Server Launched (08-24)

Date: 2026-08-24 (SiFive press release; HotHardware 12:23 EDT = 08-25 00:23 Beijing)　Sources: SiFive press release, HotHardware, HPCwire

At Hot Chips 2026, SiFive launched the BigSky SF-2U870 data center development platform, billed as the world’s first enterprise-grade, rack-deployable 2U RISC-V server: 32-core P870-D @2GHz, 256GB DDR5-5600, 3.84TB U.2 NVMe, 10/25Gbps OCP 3.0 networking, 64 lanes of PCIe Gen5 expansion (capable of accommodating dual-width GPUs and dedicated accelerators), RVA23 compliant; out-of-the-box support for Ubuntu 26.04 LTS and RHEL 10; targeting hyperscale cloud providers, chip vendors, and software vendors for enterprise software porting, workload tuning, and pre-tapeout validation of in-house chips. Already shipping in limited quantities (the company says “demand exceeds supply”; CEO Patrick Little: “RISC-V entering the data center is no longer a distant vision”). Key detail: SiFive is partnering with NVIDIA to port CUDA and plans to integrate NVLink Fusion into future platforms; CUDA already runs on BigSky, serving as the head node for modern LLM workloads on NVIDIA GPUs — the first time RISC-V hardware has had this capability.

2.2 IAR and Neusoft Reach Forge Strategic Partnership: Filling the RISC-V Automotive Toolchain Gap (08-24/25 reports)

Date: 2026-08-24/25 reports (EET-China 08-25 00:17 Beijing; the two parties signed on 08-20 in Shanghai)　Sources: BigGo Finance, EET-China

Embedded toolchain vendor IAR and Neusoft Reach signed a strategic partnership: focused on deep integration of NeuSAR OS with IAR development tools, providing integrated software and toolchain solutions for domestic development scenarios, and advancing the fusion of the AUTOSAR software ecosystem with RISC-V automotive-grade chips; the two parties will jointly build a complete toolchain spanning “chip—basic software—application development,” bridging the toolchain gap in RISC-V automotive-grade development and accelerating its large-scale deployment in the automotive industry. Note: the signing took place on 08-20, with reports on 08-24/25 falling within this window — first inclusion; Neusoft Reach is a leading vendor of the domestic automotive-grade basic software NeuSAR, and IAR has previously supported SiFive’s automotive-grade E7A/S7A cores.

2.3 Andes D23-SE Achieves ISO 26262 ASIL-B/ASIL-D Functional Safety Certification (08-24 report)

Date: 2026-08-24 report (New Electronics 18:42 Beijing; original announcement 08-18)　Sources: New Electronics, andestech.com

The AndesCore D23-SE processor has received ISO 26262 ASIL-B and ASIL-D dual-level functional safety certification (development process compliant with Parts 2/4/5/7/8). The D23-SE is a three-stage pipeline, partially dual-issue, energy-efficiency-oriented safety core covering ECU/DCU scenarios such as anti-lock braking, tire pressure monitoring, airbags, and motor drive control; the certification makes it part of Andes’ complete automotive-grade safety core portfolio alongside the N25F-SE/D25F-SE/D45-SE. Note: the original announcement was on 08-18 (outside the window); this window captures the New Electronics report — first inclusion.

2.4 LilyGo T-Display K230 Kit: Tech Times Reports Current Ubuntu Cannot Run on It (08-24/25)

Date: 2026-08-24/25 (Tech Times 08-25 03:48 Beijing)　Source: Tech Times (gnews)

Tech Times reported on the LilyGo T-Display K230 Kit under the headline “RISC-V AI pocket computer turned away by current Ubuntu” (CoreSet ~$150, Kendryte K230 dual-core RISC-V + ESP32-S3-R8 coprocessor, keyboard and LoRa optional). This is secondary coverage of the 08-21 launch event; the new detail is that current Ubuntu distributions cannot run on it (requiring dedicated Linux/RTOS images), confirming that distro support for edge RISC-V terminals remains a weak point — a follow-up observation point for this product line (in contrast to the “out-of-the-box Ubuntu/RHEL” on the server side in 2.1).

III. Domestic Team Updates and Deep Dives

3.1 XiangShan: COVE/MPT Fixes Continue to Converge, Multi-Track Progress on Performance and Memory Subsystems (08-24~25)

Date: 2026-08-24 10:19 ~ 08-25 07:12 Beijing (committer time), 19 commits within the window　Source: OpenXiangShan/XiangShan, GitHub commit search

19 commits across the main XiangShan repo and companion repos within the window, categorized by direction:

  • COVE confidential computing convergence: fix(MMU, COVE): fix mpt walker bug, pre-flush transaction not properly cleaned (#6314) — fixes the MPT walker’s pre-flush transaction not being properly cleaned up; fix(mpt): correct mfence operand decoding (#6400) — corrects mfence operand decoding. Continuing the CoVE/MPT (memory protection table) track reported on 08-24, implementation has entered the detail-convergence phase;
  • AME matrix extension verification: feat(ame): add mcfg state comparison to DiffTest (#944) — adds AME matrix configuration state comparison to differential testing, strengthening the matrix extension verification system;
  • Memory and performance: feat(extLLC): support external LLC to v3 (#6384), feat(openLLC): enlarge openLLC to 32MB (#6401) (open LLC expanded from 16MB to 32MB), feat(prefetch): add L3 prefetch path for stash prefetch (#6274), feat(MMU): improve performance counters (#6383);
  • Verification/engineering: difftest v2→v3 port (#6387), globalmem C++11 syntax compatibility, GSIM build duration recording, etc.

Significance: XiangShan has moved from “functional bring-up” into a dual-track phase of “performance wrap-up + confidential computing convergence”; work such as LLC expansion, L3 prefetch, and MMU performance counters shows performance tuning is the current main rhythm, with AME matrix extension verification advancing in parallel.

3.2 SpacemiT: New Video Decoding API and Developer Tool Documentation Updates (08-24)

Date: 2026-08-24　Source: spacemit-com/mpp, spacemit-com/docs-chip, spacemit-com/docs-tool

6 commits within the window: the mpp (media processing platform) repo added a video decoder latest-frame dequeue API (vdec fetches the latest frame, benefiting low-latency video/machine vision scenarios); docs-chip updated the P3 module operating temperature range (#205); docs-tool’s Spacemit Studio developer tool bilingual guide and screenshots updated (#44/#45). Overall routine polishing of drivers and documentation, with no major kernel mainline moves; K1/K3 ecosystem observation should follow the official mainline and operator ecosystem.

3.3 ESWIN Computing: Hong Kong IPO Disclosure Shows Cumulative Losses Exceeding RMB 5.2 Billion (08-25)

Date: 2026-08-25 (Sohu Finance 08:20 Beijing, end of window)　Source: Sohu Finance (gnews)

According to Sohu Finance citing the prospectus disclosure: ESWIN Computing has cumulative losses exceeding RMB 5.2 billion, with its top five customers accounting for over 80% of revenue (88.7%/90.7%/88.5% in 2022/2023/2024 respectively), and core product unit prices declining; the company is advancing a Hong Kong IPO. ESWIN Computing is a leading domestic RISC-V chip design company (based on the RISC-V architecture, with business covering two major lines: intelligent terminals and interconnect computing, the latter targeting automotive, robotics, and industrial scenarios). Its commercialization progress and customer concentration are important samples for observing the profitability model of leading domestic RISC-V companies. Note: data is sourced from media reports and prospectus summaries, subject to official disclosure documents; the report time falls at the end of this window and is included as an in-window event.

3.4 Routine Observation of T-Head/Nuclei/StarFive + HICOOL RISC-V+AI Challenge Semifinals (08-24)

Date: 2026-08-24　Source: GitHub org commit search (24h window), ncsti.gov.cn (gnews)

  • XUANTIE-RV (T-Head): 1 commit — test suite update in the damo-rv-priv-ats repo (#24), small-step maintenance in DAMO’s RISC-V Priv ATS direction; on the commercial side, continuing the 08-20/21 earnings-season statements (Zhenwu M890 with 650 customers, second-generation chip tape-out in H2), with no new in-window events;
  • Nuclei-Software (Nuclei): 0 commits, silent;
  • starfive-tech (StarFive): 0 commits, silent (Dubhe-100 SDK still not released, continuing the judgment from the 08-20 report);
  • eswincomputing (ESWIN Computing): 0 commits (silent on the open-source side; see 3.3 for IPO developments on the commercial side);
  • espressif (Espressif): 69 commits, but all newly added boards are ESP32-S3 (Xtensa core, not RISC-V) plus routine maintenance such as CI/CVE exclusion lists, with no RISC-V core-specific work;
  • HICOOL 2026 RISC-V+AI Collaborative Innovation Challenge semifinals successfully held in Beijing Yizhuang (ncsti.gov.cn 08-24 official report; competition started 08-21, qualifiers advance to the finals) — continuing the dense rhythm of domestic RISC-V+AI competitions and industry organization over the past two weeks (Dishui Lake Forum, Nanjing RISC-V Collaborative Innovation Alliance, HICOOL series).

IV. Special Focus: Embodied Intelligence and Robotics

4.1 No New Dedicated News: Continued Observation of Edge-Side Compute and Robotics Scenarios (08-24)

Date: 2026-08-24　Source: gnews robotics-specific queries (“risc-v” robot when:3d, embodied intelligence RISC-V when:7d), Observer (gnews)

Robotics-specific queries within the window only hit old news from 08-18~21 (edge-side RISC-V breakthrough thesis, Renesas embodied intelligence positioning, SpacemiT K3 mass production running a half-marathon), judged as a day with no new dedicated news. Related threads:

  • ICDIA 2026 closing report (Observer 08-24): the conference featured an embodied intelligence special session and an AI robotics exhibition area, with multiple parties discussing the path “from cognitive intelligence to physical execution landing” — a follow-up to the event already reported on 08-23; embodied intelligence is now a fixed topic at domestic IC conferences;
  • Edge-side compute decentralization trend continues: SpacemiT K1/K3 vision matrix, K230 Kit, ESP32-S31 Linux-ification, etc. continue to expand the boundaries of RISC-V devices carrying AI/robotics workloads; ESWIN Computing’s official website positions its interconnect and computing chips as “mainly used in automotive, robotics, and industrial scenarios, enabling agents with perception, processing, and execution capabilities,” and its IPO disclosure (3.3) shows extremely high customer concentration in this business line;
  • New variable on the server side: BigSky + CUDA (2.1) provides a new RISC-V option for the cloud training/inference foundation of embodied intelligence, worth tracking as a follow-up point.

V. Summary and Trend Observations

  1. RISC-V serverization has entered the “physical delivery” phase: BigSky 2U rack server limited in-stock availability + CUDA actually running (as head node for NVIDIA GPU LLM workloads) + NVLink Fusion roadmap, combined with Linux 7.3 server feature extensions (QoS identification/counter delegation/CFI) and ISO standardization progress — the data center “last mile” software stack is being densely filled in;
  2. NVIDIA CUDA support has moved from 2025 statements to 2026 Hot Chips technical requirement refinement (RVA23, PCIe coherency, P2P); “server-class CPU + platform” is a hard threshold, directly benefiting high-performance cores like P870-D and the RVA23 server specification ecosystem;
  3. Domestic divergence continues: XiangShan advances on dual tracks (COVE convergence + performance/memory polishing, 19 commits, most active within the window); SpacemiT routine drivers/documentation; ESWIN Computing’s Hong Kong IPO disclosure shows cumulative losses exceeding RMB 5.2 billion and high customer concentration — the commercialization pressure on leading domestic RISC-V design companies is becoming explicit and requires continued tracking;
  4. Automotive-grade ecosystem reinforcement: IAR×Neusoft Reach toolchain collaboration, Andes D23-SE ASIL-B/D certification, combined with ESWIN EAI8800 (dual certification in July) — the RISC-V automotive-grade chain of “IP—toolchain—foundational software—chip” is gradually closing, and AUTOSAR ecosystem migration to RISC-V is accelerating;
  5. Open-source activity rebounds: CPython tier 3, multiple Linux 7.3 extension merges, rising HN discussion on CUDA-on-RISC-V (68 points), contrasting with the calm of the past two days; official Python support fills a key link in the AI software stack.

Limitations note: BigSky performance data and CUDA operation details are based on vendor press releases, with no independent evaluation yet; ESWIN Computing financial data is sourced from media reports and prospectus summaries, subject to official disclosure documents; the ISO/IEC DIS 26791-1 page is anti-scraping protected and cannot be directly fetched, so the specific technical scope is subject to the ISO official website; XiangShan commit content is based on commit messages and does not cover microarchitecture-level verification details; the IAR×Neusoft signing was an 08-20 event whose coverage entered the window, and the event itself did not occur within the window.

Appendix: Complete Source List

No. Event Source Link
1 CPython RISC-V tier 3 official support blog.python.org, HN
2 Linux 7.3 adds RISC-V extensions Phoronix
3 Hot Chips 2026: CUDA targets RISC-V Chips and Cheese, HN
4 ISO/IEC DIS 26791-1 (RISC-V ISA manual) iso.org/standard/94578, HN
5 SiFive BigSky SF-2U870 server SiFive press release, HotHardware, HPCwire (gnews)
6 IAR × Neusoft Reach automotive-grade toolchain partnership BigGo Finance, EET-China (gnews)
7 Andes D23-SE ISO 26262 certification New Electronics (gnews), andestech.com
8 LilyGo T-Display K230 Kit (secondary pickup of the 08-21 event) Tech Times (gnews)
9 19 commits in the XiangShan window GitHub commit search
10 6 commits from SpacemiT spacemit-com org
11 ESWIN Computing Hong Kong IPO disclosure Sohu Finance (gnews)
12 HICOOL 2026 RISC-V+AI Challenge semifinals ncsti.gov.cn (gnews)
13 ICDIA 2026 concludes successfully (embodied intelligence session follow-up) The Observer (gnews)
14 Commit search across organizations (8 orgs) GitHub Search API

Supplementary Query Verification Table (24h window, Beijing time 08-24 08:18 ~ 08-25 08:18)

Source/Query Verification Result
fetch_news.py 24h candidates (20 items) 8 valid main threads: CPython, Linux 7.3, CUDA/RISC-V, ISO DIS, BigSky (dual coverage from HPCwire/HotHardware), IAR×Neusoft Reach, Andes D23-SE, K230 Kit; Nvidia’s Korean media coverage corroborates the CUDA story; the api-evangelist series repos are bot-generated profiles (noise, excluded), grain/pzaino profiles are unrelated projects (excluded)
gnews “RISC-V when:1d” bare query (6 items) Valid corroboration: NVIDIA CPU expansion strategy (South Korea’s Maeil Business Newspaper), IAR×Neusoft Reach (EET-China); HICOOL semifinals (ncsti official), ICDIA concludes (The Observer); Orange Pi Zero 4 is Allwinner A733 (ARM core, mislabeled by Sina keywords, excluded); Telink is a general financial report (not RISC-V-specific, excluded)
gnews vendor queries (SiFive/Andes/Milk-V when:3-7d) SiFive when:3d empty (BigSky captured via the English original site/HN channels); Andes when:3d empty (New Electronics article captured via fetch English sources); Milk-V hit old Linux kernel news (excluded)
gnews Chinese team queries (T-Head/XiangShan/SpacemiT/ESWIN/Nuclei/Sophgo/StarFive when:7d) T-Head hit old earnings-season news from 08-20/21 (trend reference); XiangShan only old whitepaper news from 08-20; SpacemiT was old K3 half-marathon news; ESWIN hit Hong Kong IPO disclosure (included in 3.3) plus HICOOL/ICDIA; Nuclei/Sophgo were entirely stock market/gambling noise (Hong Kong-listed company “智算能建” mismatched on “算能”, excluded); StarFive was old Dubhe-100 news from 08-18 (already reported)
gnews robotics-specific queries (“risc-v” robot when:3d, embodied intelligence RISC-V when:7d) All old news from 08-18~21 (edge-side breakthrough thesis, Renesas, SpacemiT K3 half-marathon) and gambling SEO noise, no new items (see 4.1)
HN (Algolia, 36h) 3 items: CPython (4 points), CUDA Targets RISC-V (68 points/9 comments), ISO DIS 26791-1 (2 points) — all included, discussion activity the highest in the past three days
GitHub organization commit/repo search (8 orgs) XiangShan 19 commits (included in 3.1), SpacemiT 6 commits (included in 3.2), T-Head 1 commit (damo-rv-priv-ats test suite), Espressif 69 commits (all Xtensa boards/routine, no RISC-V-specific items); Nuclei/ESWIN/StarFive 0 commits