Research window: Past 24 hours (2026-08-23 08:18 ~ 2026-08-24 08:18 Beijing Time) Sources: HN (Algolia API), Google News RSS aggregation (English + Chinese, via proxy), direct scraping of Notebookcheck / Zhongguo Jiangsu Wang (Jiaohuidian) original sites, GitHub API (commit search and repo pushes for Espressif / XiangShan / SpacemiT / T-Head / Sophgo / Nuclei / ESWIN / StarFive organizations, see appendix)

Today’s Index

  • I. Open-Source Community and Software Ecosystem
    • Sedna: Pure-Java RISC-V emulator resumes development, evolving toward a multi-architecture framework (08-23)
    • Arduino ESP32 core adds optional SHA-256 verification for OTA firmware (08-24)
  • II. Product and Ecosystem Developments
    • No new standalone items: T-Display K230 Kit is a secondary propagation of the 08-21 event (08-23)
  • III. Domestic Team Developments and Deep Dives
    • XiangShan: Two fixes to the COVE confidential-computing MMU path merged (08-24)
    • 6th Integrated Circuit Design Innovation Conference lands in Nanjing: RISC-V Collaborative Innovation Alliance launched (08-23)
    • Routine observations of T-Head / SpacemiT / Nuclei / ESWIN / StarFive (08-23)
  • IV. Special Chapter on Key Directions: Embodied Intelligence and Robotics
    • No new dedicated news: Conference features an embodied intelligence track and an AI robotics exhibition area (08-23)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List and Quiet-Day Checklist

I. Open-Source Community and Software Ecosystem

1.1 Sedna: Pure-Java RISC-V emulator resumes development, evolving toward a multi-architecture framework (08-23)

Date: 2026-08-23 (README updated 23:11 Beijing; active development since 08-21)　Source: github.com/fnuecke/sedna

The pure-Java RISC-V emulator Sedna, born in 2020 (rv64imacfd + Zifencei, supports S-mode, can boot Linux, passes all riscv-tests cases, supports machine-state serialization, published on Maven Central), resumed active development in this window: the author migrated the old Z80 emulator into the Sedna framework (generalized instruction decoder generator, disk device migration, Z80 board-level integration), with the README updated at 08-23 23:11 (Beijing Time). The project’s positioning is evolving from a “single-architecture RISC-V emulator” toward a “multi-architecture emulation framework” — the decoder generator now also serves Z80 as a proof of concept, giving the JVM ecosystem an actively maintained RISC-V emulator option (beyond QEMU).

1.2 Arduino ESP32 core adds optional SHA-256 verification for OTA firmware (08-24)

Date: 2026-08-24 (03:38 Beijing, committer time)　Source: espressif/arduino-esp32 PR #12824

Espressif’s arduino-esp32 core merged feat(update): add optional SHA-256 checksum for incoming firmware (#12824): adding optional firmware SHA-256 verification to the OTA update flow, strengthening firmware integrity validation (against download corruption/tampering). Both the ESP32-C series (C3/C5/C6/C61 and other RISC-V cores) and the Xtensa series benefit; this is routine hardening of Espressif’s software ecosystem, with no breaking changes.

II. Product and Ecosystem Developments

2.1 No new standalone items: T-Display K230 Kit is a secondary propagation of the 08-21 event (08-23)

Date: 2026-08-23 (Notebookcheck 22:33 Beijing)　Source: Notebookcheck

There were no brand-new product launches in the window. Notebookcheck reported on the T-Display K230 Kit under the headline “LilyGo K230: Versatile RISC-V mini system launches with keyboard option and LoRa” (CoreSet at about $150, optional matching keyboard, LoRa off-grid communication, Kendryte K230 dual-core RISC-V SoC + ESP32-S3-R8 coprocessor, 4.1-inch AMOLED, HDMI/Ethernet/USB/3.5mm audio), which is the same product event as the 08-21 LinuxGizmos report (already covered in the 08-22 report, item 2.2), and is not re-included per deduplication rules. Its positioning of “keyboard + LoRa emergency communication, offline teaching” and the ESP32-S3-R8 coprocessor details can serve as follow-up tracking points for this product line.

III. Domestic Team Updates and Deep Dives

3.1 XiangShan: Two Fixes to the COVE Confidential Computing MMU Path Merged (08-24)

Date: 2026-08-24 (00:02 Beijing, committer time)　Source: OpenXiangShan/XiangShan PR #6299, PR #6300

Two commits landed in the main XiangShan repository during the window, both targeting the MMU implementation of COVE (Confidential VM Extension):

  • #6299 fix(MMU, COVE): reject out-of-range Smmpt addresses: Previously, Smmpt43 requests exceeding the 43-bit address range were not rejected by MPTCache and were instead treated as cache misses and sent to the miss queue/table walker, rather than returning an access fault. The fix defines the PA width for Smmpt43 / Smmpt52 and the maximum legal PPN for each mode (43-bit: 0x007fffffff; 52-bit: 0xffffffffff), validates the request PPN at the stageCheck pipeline stage, returns accessFault via respHit for out-of-range requests, suppresses respMiss to prevent table walks, and clears permission / NAPOT / contiguous permission / MPT-level metadata on range faults, as well as clearing the range-fault register on cache flush;
  • #6300 fix(MMU, COVE): fix bug for mpt miss queue: The current MPT miss queue implementation violates the Decoupled protocol (twReq.valid is not gated by ready). Although no functional request loss has been observed, it was fixed for protocol compliance.

Significance: XiangShan is one of the few RISC-V open-source high-performance processor projects advancing the CoVE/MPT (Memory Protection Table) confidential computing path. Both fixes are of a “protocol compliance polish” nature, indicating that its COVE implementation has moved past functional bring-up and entered a detail-convergence phase—consistent with the overall recent cadence of a “performance wrap-up period” (a phase of fine-grained work following the convergence of major items such as branch prediction/AIA).

3.2 Sixth Integrated Circuit Design Innovation Conference Lands in Nanjing: RISC-V Collaborative Innovation Alliance Launched (08-23)

Date: 2026-08-23 (Xinhua Daily/Jiaohuidian report 18:50 Beijing)　Source: Jiangsu News/Jiaohuidian

The Sixth Integrated Circuit Design Innovation Conference and Application Exhibition, themed “AI Empowers, Intelligently Creating the Chip Future,” landed for the first time in Nanjing Jiangbei New Area: 2 main sessions, 8 thematic sessions, 5 major themed exhibition zones, over 100 expert and enterprise presentations, approximately two thousand professional attendees, with participation from UNISOC, Empyrean, Alibaba, Intel Research, and others. RISC-V-related highlights:

  • The RISC-V Collaborative Innovation Alliance was launched in tandem, alongside the unveiling of the Chiplet Collaborative Innovation Center, building a platform for technical exchange and industrial cooperation for open-source chips and advanced packaging;
  • Thematic sessions covered IC design innovation, automotive chip localization (the first domestic quantitative standard for automotive-grade chip health, “AsaChi,” was interpreted), advanced packaging, the RISC-V open-source ecosystem, home appliance chip innovation (Haier/Hisense/TCL), embodied intelligence, industry-education integration, and investment/financing matchmaking;
  • The “2026 Strong Chip List” was released, and the 2026 China Graduate IC Innovation Competition · EDA Elite Challenge was launched (talent pipeline development).

Background: The host location, Jiangbei New Area, has already gathered over 600 enterprises across the full IC supply chain. The industry is shifting toward system-level innovation characterized by “AI empowerment + architectural innovation + advanced packaging + open-source ecosystem collaboration”; the launch of the RISC-V Collaborative Innovation Alliance is another signal of the industrialization and organization of open-source processors (in the past two weeks alone, there have been a dense series of actions including the Dishui Lake RISC-V Industry Forum and the HICOOL 2026 RISC-V+AI Collaborative Innovation Challenge semifinals).

3.3 Routine Observation of T-Head/SpacemiT/Nuclei/ESWIN/StarFive (08-23)

Date: 2026-08-23　Source: GitHub org commit search (24h window)

  • XUANTIE-RV (T-Head): 0 commits, silent on the open-source side; on the commercial side, information has been dense over the past 3 days (08-20/21)—the earnings call disclosed that Zhenwu M890 has served over 650 external customers (covering 20+ industries), AI chips will continue to ramp in H2, and the second-generation chip is expected to tape out and yield in H2 (events outside the window, for trend reference, see summary);
  • spacemit-com (SpacemiT): 0 commits, silent (the K1/K3 operator ecosystem follows the official mainline);
  • Nuclei-Software (Nuclei): 0 commits, silent;
  • eswincomputing (ESWIN Computing): 0 commits, silent;
  • starfive-tech (StarFive): 0 commits, silent (the Dubhe-100 SDK is still not released, continuing the judgment from the 08-20 report);
  • espressif (Espressif): arduino-esp32 OTA SHA-256 verification merged (see 1.2); the rest are routine maintenance such as NVD vulnerability database sync and CI improvements (esp-idf had 0 core commits in this window), and no new pushes to the three Linux BSP repositories.

IV. Special Chapter on Key Directions: Embodied Intelligence and Robotics

4.1 No New Dedicated News: Conference Features an Embodied Intelligence Track and AI Robotics Exhibition Zone (08-23)

Date: 2026-08-23　Source: gnews robotics-specific queries (“risc-v” robot when:3d, embodied intelligence RISC-V when:7d), Jiaohuidian

Robotics-specific queries during the window only hit previously reported old items (Alibaba 27B, etc.); Chinese-language “embodied intelligence RISC-V” queries mostly hit old news from 08-18~21 (SpacemiT K3 mass production running a half-marathon, Renesas embodied intelligence positioning, etc.) and gambling SEO noise, judged to be a day with no new dedicated news. Related threads:

  • The Nanjing conference opened a dedicated ecosystem session for the embodied intelligence track and set up an AI robotics exhibition zone, with multiple parties discussing the technical path to “connecting cognitive intelligence to physical execution and deployment”—embodied intelligence is now a fixed agenda item at domestic IC conferences;
  • Continuation of yesterday’s main news: the ESP32-S31 Linux BSP (reported 08-22) remains the only RISC-V topic on HN within 36 hours (discussion heat continues); the T-Display K230 Kit’s “keyboard + LoRa off-grid communication” form factor (08-21 event) was re-circulated by Notebookcheck, confirming rising interest in the “pocket-sized RISC-V terminal + off-grid communication” scenario;
  • Trend line continues: edge/endpoint compute continues to be pushed downward (SpacemiT K1 vision model matrix, KEO edge LLM, ESP32-S31 Linux-ification, K230 Kit), the capability boundary of RISC-V devices carrying AI/robotics workloads continues to expand outward, and hardware and kernel actions remain the most reliable observation anchors.

V. Summary and Trend Observations

  1. The most technically significant development in the window is the XiangShan COVE confidential computing MMU fix (Smmpt43/52 out-of-range rejection + MPT miss queue protocol compliance); the implementation of the open-source high-performance RISC-V processor on the CoVE/MPT path has entered a detail-convergence phase;
  2. RISC-V ecosystem organization is accelerating: the launch of the RISC-V Collaborative Innovation Alliance at the Nanjing conference, the unveiling of the Chiplet Collaborative Innovation Center, combined with the Dishui Lake Forum and the HICOOL RISC-V+AI Challenge over the past two weeks, industrial collaboration platforms are landing densely, and open-source processors are moving from “technology community” to “industry alliance”;
  3. The open-source side is quiet: the Sedna simulator restart (multi-architecture frameworkization) and arduino-esp32 OTA SHA-256 hardening are the only new open-source developments; HN had only 1 item in 36h (ESP32-S31 old news continuing to trend), and there were no major new events in the English-language media window;
  4. Divergence among major domestic teams continues: XiangShan active (2 COVE fixes), Espressif routine (Arduino ecosystem hardening), the other 5 organizations at 0 commits; T-Head silent on open source but dense on commercialization information (Zhenwu M890 with 650 customers, H2 ramp, second-generation chip tape-out imminent—statements from the 08-20/21 earnings season, not events within the window);
  5. The product side is quiet: the T-Display K230 Kit is a re-circulation of the 08-21 event, with no brand-new product launches within the window; the ESP32-S31 mass production cadence and the progress of Linux-side WiFi/Bluetooth support remain points to watch going forward.

Limitations note: The content of the XiangShan COVE commits is based on PR descriptions and does not cover microarchitecture-level verification details; the Nanjing conference’s “RISC-V Collaborative Innovation Alliance” is a launch announcement, and its membership composition and operating mechanism have not yet been disclosed; Sedna is a small-scale open-source project maintained by an individual, not an organization-level development; T-Head’s commercialization data originates from reports related to the earnings call (08-20/21), not new events in this window, and is provided for trend reference only.

Appendix: Complete Source List

No. Event Source Link
1 Sedna emulator resumes development (README update + Z80 integration) github.com/fnuecke/sedna
2 arduino-esp32 optional OTA SHA-256 verification github.com/espressif/arduino-esp32/pull/12824
3 T-Display K230 Kit second report (08-21 event) Notebookcheck
4 XiangShan COVE/MMU fixes (#6299/#6300) github.com/OpenXiangShan/XiangShan/pull/6299, pull/6300
5 6th Integrated Circuit Design Innovation Conference (Nanjing, RISC-V Collaborative Innovation Alliance launched) jsnews.jschina.com.cn
6 Commit search across organizations GitHub Search API

Quiet-Day Source Verification Table (24h window, Beijing time 08-23 08:18 ~ 08-24 08:18)

Source/Query Verification Result
fetch_news.py 24h candidates (6 items) 2 valid: sedna (included as 1.1), LilyGo K230 Notebookcheck (second-wave coverage of the 08-21 event, excluded — see 2.1); Samsung/ServeTheHome, Bangalore Mirror, grain, pzaino profile are noise (excluded)
gnews “RISC-V when:3d” (13 items) Only the Notebookcheck K230 Kit falls within the window (second-wave coverage); the rest are events already reported on 08-21~22 (ESP32-S31, KEO, Alibaba 27B) or unrelated noise
gnews vendor queries (SiFive/Milk-V/SpacemiT/SOPHGO/StarFive/Andes when:3-7d) All hits are old news or noise: Andes matched Peru earthquake/Chile AES energy storage/universities; SiFive matched Samsung/SK Hynix/IPO lists; StarFive only old Dubhe-100 news (reported 08-20); SpacemiT empty; SOPHGO/Milk-V matched old Linux 7.2/7.3 news
gnews Chinese team queries (T-Head/XuanTie, XiangShan processor, ESWIN when:7d) T-Head matched old earnings-season news from 08-18~21 (Zhenwu M890 with 650 customers, Qwen3.8-27B Day0, expectations of second-gen chip tape-out — none within the window, kept as trend reference); XiangShan/ESWIN matched old conference news and stock-market noise
gnews robotics-specific (“risc-v” robot when:3d, embodied intelligence RISC-V when:7d) Only old news (Alibaba 27B, SpacemiT K3 half-marathon, Renesas embodied intelligence) and gambling SEO noise, nothing new (see 4.1)
HN (Algolia, 36h) Only 1 item: ESP32-S31 Linux BSP (reported 08-22, already included), no new discussion
GitHub org commit/repo search (8 orgs) XiangShan 2 commits (COVE/MMU, included as 3.1), espressif arduino-esp32 1 commit (included as 1.2) + routine NVD/CI; SpacemiT/T-Head/Nuclei/ESWIN/StarFive 0 commits