Research window: Past 24 hours (2026-08-20 08:19 ~ 2026-08-21 08:19 Beijing Time) Sources: HN (Algolia API), Google News RSS aggregation (English, via proxy), CNX Software direct crawl, The Register original articles, Jon Peddie Research / EE Times / design-reuse, GitHub API (XiangShan/T-Head/SpacemiT/Sophgo/Nuclei/ESWIN/StarFive organization commit search and repo pushes), vendor official sites (see appendix)

Today’s Index

  • I. Open Source Community and Kernel/Release Updates
    • Linux 7.2 release roundup: RISC-V NR_CPUS raised to 256, ESWIN enters defconfig (08-21)
    • NetBSD 11 lands 64-bit RISC-V support (08-20)
  • II. Product and Ecosystem Updates
    • Andes closes Condor Design Center, Cuzco data-center-class core IP returns to parent company (08-17/08-20)
  • III. Domestic Team Updates and Deep Dives
    • XiangShan: 20 commits in 24 hours, WritebackQueue and TAGE performance optimizations (08-20)
    • SpacemiT: K1 software stack v2.2.11 update (08-20)
    • T-Head/Nuclei/ESWIN/StarFive/Sophgo routine observation (08-20)
  • IV. Special Focus: Embodied Intelligence and Robotics
    • No new dedicated news in window: underlying progress continues (08-20)
  • V. Summary and Trend Observations
  • Appendix: Complete Source List and Quiet-Day Checklist

I. Open-Source Community and Kernel/Release Updates

1.1 Linux 7.2 Release Roundup: RISC-V NR_CPUS Raised to 256, ESWIN Enters defconfig (08-21)

Date: 2026-08-16 (kernel release, LKML) / 2026-08-21 (CNX architecture-level roundup, 06:00 Beijing)　Source: CNX Software, Linux Journal

Linus Torvalds released Linux 7.2 on 08-16 (LKML), with CNX publishing an architecture-level roundup on 08-21; RISC-V updates were dense. General highlights: cache-aware task scheduling (threads of the same process co-located by LLC domain), a CFS-inspired Fair GPU scheduler, USB4STREAM direct streaming, and phase four of the swap table. RISC-V specifics:

  • NR_CPUS 64-bit default raised to 256 — the official rationale points directly at domestic many-core machines: SpacemiT already ships an 80-core RVA23 server, and the dual-socket SG2042-based Sophgo Pisces reaches 128 cores, so the default of 64 is no longer sufficient;
  • ESWIN SoC added to the RISC-V defconfig — a domestic vendor entering the mainline default configuration, a higher bar than ordinary driver inclusion;
  • T-Head TH1520: PWM fixes, WiFi enabled on both the BeagleV Ahead and Lichee Pi 4a boards;
  • SpacemiT: SPI/thermal drivers and I2C enablement added for K1, USB2 PHY and ASoC drivers added for K3, reboot cell added for the P1 chip; extensive board-level peripheral enablement for K1 (Milk-V Jupiter eMMC, Muse Pi Pro EEPROM/PCIe/QSPI/USB, OrangePi R2S PMIC/USB3, OrangePi RV2 full peripherals); two new K1 boards added, CoM260-IFX and DeepComputing FML13V05;
  • Sophgo: bindings added for Milk-V Duo S; SG2042/SG2044 device tree fixes (CPU addresses converted to hexadecimal, MSI actually only 16 interrupts, PCIe RC marked cache-coherent);
  • StarFive: the JH8100 interrupt controller was renamed and reworked into the JHB100 version after the chip was discontinued without reaching mass production; JH7110 added to the SiFive ccache non-standard cache operation list (GPU DMA non-coherent); JHB100 gained new clint bindings and SGMII GMAC support;
  • Core fixes: kexec_file early boot with large memory, unconditional sfence.vma, kfence false-positive fix, CFI vDSO patches, ftrace_graph_ret_addr, BUILDTIME_MCOUNT_SORT to reduce boot overhead, and more.

The 7.3 merge window has opened with the release (Linus says 40 PRs are already pending); Phoronix reports that 7.3 will phase out legacy 32-bit ARM platforms on a large scale (an ARM-side restructuring, with impact on RISC-V yet to be seen). This roundup confirms that the Linux mainline is laying the groundwork at scale for “80-128 core domestic RISC-V servers.”

1.2 NetBSD 11 Lands 64-bit RISC-V Support (08-20)

Date: 2026-08-20 (The Register report 21:45 Beijing; HN in parallel)　Source: The Register, HN discussion

NetBSD’s 19th major release, 11.0 (released at the end of July), received a lengthy review from The Register: it adds 64-bit RISC-V support (a Tier II platform, targeting QEMU virtualization environments), making NetBSD the third BSD-family operating system after Linux and FreeBSD to provide mainline RISC-V support. 11.0 also brings: a MICROVM-specific kernel (roughly 10 ms cold boot for x86 guests, measured on 2020s-era processors), improved POSIX.1-2024 and C23 compliance, enhanced Linux syscall compatibility, Xen/QEMU runtime optimizations, 52 Tier II platforms and 9 Tier I platforms. The review also notes that NetBSD retains its “old-school” style: a text-based sysinst installer, manual edits to /etc/rc.conf, and scarce commercial drivers. The significance for the RISC-V ecosystem: the BSD camp’s RISC-V support is now filled in, landing first in virtualization scenarios (QEMU).

II. Product and Ecosystem Updates

2.1 Andes Shuts Down Condor Design Center, Cuzco Data Center-Class Core IP Returns to Parent (08-17/08-20)

Date: 2026-08-17 (Jon Peddie Research first report) / 2026-08-20 (EE Times follow-up, 06:00 Beijing)　Source: Jon Peddie Research, design-reuse repost, EE Times

Andes Technology has formally closed Condor Computing, its high-end design center in Austin, Texas (founded 2023-03, nearly 100 people, over 85% in R&D). Condor carried Andes’ flagship project for breaking into data center-class RISC-V: the Cuzco core — RVA23-compliant, licensable, and built on a new patented microarchitecture (deep out-of-order execution plus an unconventional time-scheduling design, disclosed at Hot Chips 2025). Current status: the Cuzco IP has returned to parent company Andes, with no further test silicon development; the team was cut from 50 to 15 and then to a single-digit number of engineers who truly understand the IP; former CEO Ty Garibay has moved to Ambiq as VP of SoC Design. The closure is part of a cost-cutting plan announced in 2026-04: Chairman and CEO Frankwell Lin acknowledged that the company expanded too quickly over the past three to four years while revenue failed to keep pace, and plans to cut operating expenses by 10-20% and reduce global headcount from 480 to about 450 (EE Times estimates it is already around 400).

Industry significance: Jon Peddie Research analyst David Harold said plainly that this is “a setback for Andes’ high-end ambitions and a retreat in RISC-V’s effort to establish a credible Arm/x86 alternative in the data center.” This stands in contrast to 1.1, where the Linux mainline is paving the way for many-core servers — the software side is accelerating, while the IP vendor camp is reshuffling and contracting.

III. Domestic Team Activity and Deep Dive

3.1 XiangShan: 20 Commits in 24 Hours, WritebackQueue and TAGE Performance Optimization (08-20)

Date: 2026-08-20 (10:59 ~ 01:32 next day Beijing, committer time)　Source: OpenXiangShan/XiangShan, XiangShanLab, env-scripts

The XiangShan organization logged 20 commits within the window, with 4 substantive commits landing in the main repository (XiangShan), showing a clear performance-oriented iteration:

  • timing(WritebackQueue): use lowestIndexFirst policy (#6379) (08-20 10:59 Beijing) — writeback queue switched to a lowest-index-first scheduling policy, optimizing memory backend timing;
  • build: generate CHIRRTL only for gsim (#6374) (11:36) — build system streamlining (CHIRRTL generated only for gsim);
  • perf(Tage): optimize UseAltOnNa (#6328) (17:24) — TAGE branch predictor UseAltOnNa policy optimization;
  • fix(uart16550): expose DesignWare status register (#6385) (08-21 01:32) — UART status register exposure, improving debugging and board-level usability.

Supporting repositories: XiangShanLab added an xs bug replay script (replaying bugs by commit hash), and env-scripts received two perf_trigger fixes (#154/#155, enhancing runtime analysis logging). With sustained high-intensity merges over multiple consecutive days, this round’s focus has shifted from memory access correctness to writeback queue scheduling and branch prediction performance fine-tuning — characteristic of the architecture performance wrap-up phase.

3.2 SpacemiT: K1 Software Stack v2.2.11 Release Update (08-20)

Date: 2026-08-20 (09:07 ~ 17:25 Beijing)　Source: spacemit-com/buildroot-ext, uboot-2022.10, mpp, v2d-test

The SpacemiT organization logged 22 commits within the window, centered on the K1 software stack v2.2.11 full-package update: buildroot-ext, uboot-2022.10, and v2d-test were synchronized to v2.2.11, with K1 buildroot changing GENERIC_HOSTNAME to “K1-Buildroot” and expanding the root filesystem to 1GB (accommodating a larger software set); mpp media pipeline received two engineering refactors (stream manager moved out of the mpi interface layer, AL module build targets split), and v2d-test fixed K1 buildroot build errors. Continuing the cadence reported on 08-18 of “K1 mainline kernel 7.2 landing in Yocto via meta-riscv,” this round represents BSP full-package versioned delivery, with the media pipeline evolving toward an independently maintainable module structure.

3.3 Routine Observation of T-Head/Nuclei/ESWIN/StarFive/Sophgo (08-20)

Date: 2026-08-20　Source: GitHub org commit search (24h window)

  • XUANTIE-RV (T-Head): 0 commits, silent (C950 performance narrative covered in 08-19/08-20 reports, no new open-source activity);
  • Nuclei-Software (Nuclei): 0 commits, silent;
  • eswincomputing (ESWIN): 0 commits — but ESWIN SoC has entered the Linux 7.2 RISC-V defconfig (see 1.1); its “activity” manifests in mainline inclusion rather than its own repository;
  • starfive-tech (StarFive): 0 commits, silent (Dubhe-100 SDK still unreleased, consistent with the 08-20 report assessment);
  • sophgo (Sophgo): 1 fix in the mcu repository — [fix] SM7M_MP_1_1 abnormal power-down issue caused by i2c reset (#83) (08-20 16:52 Beijing), routine maintenance for the MCU product line.

IV. Special Focus Chapter: Embodied Intelligence and Robotics

4.1 No New Dedicated News in Window: Underlying Progress Continues (08-20)

Date: 2026-08-20　Source: gnews dedicated queries (“risc-v” robot when:3d, embodied intelligence RISC-V when:3d), GitHub organization search

The gnews robotics dedicated query within the window only returned items already reported yesterday (Dubhe-100, NetBSD), with no independent new stories; the Chinese “embodied intelligence RISC-V” query returned empty. This is judged a day with no new dedicated news, but underlying progress has not stalled, directly relevant to embodied/edge compute:

  • PDMA, USB2, and Ziccrse extension enablement for SpacemiT K3 in Linux 7.2 — the peripheral foundation for robot main-control SoCs continues to be filled in on mainline;
  • XiangShan WritebackQueue scheduling policy and TAGE optimization — microarchitectural fine-tuning for low-latency response;
  • Trend continuity: the 08-19/08-20 reports already covered how both T-Head C950 (30 tok/s running Qwen3.8-27B) and StarFive Dubhe-100 have written “AI agent server/robot” into their core scenarios; this window brings no new narrative but the hardware baseline is advancing. Observation conclusion: news density in the robotics direction shows periodic decline; judgments should be based on hardware and kernel actions rather than headlines.

V. Summary and Trend Observations

  1. Linux 7.2 is a mainline milestone for domestic multi-core RISC-V servers: NR_CPUS default raised to 256 (explicitly citing SpacemiT 80-core and Sophgo Pisces 128-core), ESWIN entering defconfig, and large-scale peripheral enablement for SpacemiT K1/K3 — the coupling between mainline and domestic high-end SoCs has clearly deepened;
  2. Data-center-class IP camp reshuffling: Andes shutting down Condor and Cuzco returning to the parent company is another signal following SiFive’s contraction; the weight of the “Chinese duo” (T-Head/StarFive) in the high-end RISC-V core race rises further, with software-side paving and IP-side contraction coexisting;
  3. BSD ecosystem filling in: NetBSD 11 provides 64-bit RISC-V mainline support, marking another advance in mainstream open-source OS coverage of RISC-V;
  4. Divergent cadence among domestic teams: XiangShan (performance fine-tuning phase) and SpacemiT (v2.2.11 full-package delivery) are highly active; T-Head/Nuclei/StarFive/ESWIN repositories are silent, but ESWIN’s inclusion action is in the mainline defconfig;
  5. Explanation of the quiet day: gnews Chinese queries returned empty within the window, and vendor English queries mostly returned already-reported events; domestic activity was mainly captured through GitHub organization searches (see appendix verification table).

Limitations: Linux 7.2 RISC-V changes are based on CNX reporting and have not been verified line-by-line against the kernel changelog; Andes shutdown details (team size, headcount) are based on EE Times/JPR reporting and have not been officially confirmed by Andes (no formal announcement issued); NetBSD 11 reflects The Register’s review perspective, and the RISC-V port is Tier II (QEMU) rather than Tier I real hardware; XiangShan/SpacemiT commits are categorized by committer time, and individual commits’ author dates may predate the window.

Appendix: Complete Source List

No. Event Source Link
1 Linux 7.2 release and RISC-V architecture roundup CNX Software
2 Linux 7.2 official release coverage Linux Journal
3 NetBSD 11 lands RISC-V support The Register
4 Andes shuts down Condor (first reported by JPR) Jon Peddie Research
5 Andes shuts down Condor (design-reuse reprint) design-reuse
6 Andes cost-cutting background (EE Times) EE Times
7 XiangShan main repo commits (4) github.com/OpenXiangShan/XiangShan
8 SpacemiT v2.2.11 update github.com/spacemit-com/buildroot-ext
9 Sophgo mcu fix #83 github.com/sophgo/mcu
10 XiangShan org commit search GitHub Search API

Quiet-Day Source Verification Table (24h window, Beijing time 08-20 08:19 ~ 08-21 08:19)

Source/Query Verification Result
gnews “RISC-V when:3d” Valid: hits Linux 7.2 (included), NetBSD 11 (included), Andes Condor (included); the rest are events already reported yesterday (Dubhe-100 multi-source reprints, C950 Qwen, Pine64, Adafruit debate) or irrelevant noise (ETH costs, ChatGPT teen version), deduplicated
gnews Chinese team queries (T-Head/XiangShan/SpacemiT/Sophgo/Nuclei/ESWIN when:7d) All empty hits; no new items within the window for the zh-CN region; domestic developments covered mainly via GitHub org searches
gnews vendor queries (SiFive/Milk-V/SpacemiT/SOPHGO/”Andes Technology”/StarFive when:3-7d) SiFive/SpacemiT empty; Milk-V/SOPHGO hit the Phoronix 7.3 ARM core-dropping article (ARM topic, excluded); Andes hit the Condor closure (included); StarFive all Dubhe-100 reprints (already reported)
gnews “RISC-V Summit when:7d” Empty hits
gnews robotics-specific (“risc-v” robot when:3d, embodied intelligence RISC-V when:3d) Only items already reported yesterday, no new additions (see 4.1)
GitHub org commit search (7 orgs) XiangShan 20, SpacemiT 22, Sophgo 1; T-Head/Nuclei/ESWIN/StarFive 0
GitHub topic:risc-v pushed search 7 repos, all low-star new repos/description-only repo noise, no substantive new projects
gnews “RISC-V when:1d” bare query to verify proxy Proxy working normally (when:3d returning results proves it); 1d not run separately