RISC-V Daily Intelligence Report (2026-08-19)

Research window: Past 24 hours (2026-08-18 08:20 ~ 2026-08-19 08:20 Beijing time) Sources: HN (Algolia API), Google News RSS aggregation (English + Chinese, via proxy), CNX/LinuxGizmos/Phoronix/riscv.org RSS, GitHub API (riscv official organization/XiangShan/T-Head/SpacemiT/Sophgo/ESWIN/Nuclei/ESWIN), Wccftech/The Register direct site scraping (see appendix)

I. Open-Source Community and Kernel/Release Dynamics

1.1 HAC High-Assurance Cryptography Spec: Fourth Day of Intensive Revisions — Zl→Zkl Rename Proposal, WARL Rules, Smacestatus Integration (30+ Commits)

Date: 2026-08-18 (12:05–22:26 Beijing Time)　Source: riscv/riscv-high-assurance-cryptography GitHub

The High-Assurance Cryptography (HAC, a cryptographic extension spec targeting FIPS 140-3-level implementations) repository merged 30+ commits within the window, continuing the review-convergence thrust of the previous three days and entering the “naming and structural wrap-up” phase:

Naming finalized: Changed Zl extension prefix to Zkl (Zl prefix renamed to Zkl), Added proposal for ratified names, Fixed Zlkn dependencies, Reformatted new names table — extension naming transitioning from working names to ratified names;
Semantics finalized: Defined WARL rules for aceiobuflen, aceiobuftop and acestart (WARL rules for three key CSRs), Clarify invalid aceiobuftop exception behavior, Integrate mcrstatus CSR into Smacestatus extension (mcrstatus merged into the Smacestatus extension), Clarify vector I/O replacement rules, Default CSR values out of reset;
Document structure reorganization: pseudocode examples moved to Book 4, finite-field operation definitions relocated, multiple consecutive revisions to ace-introduction.

With 80+ revisions over four consecutive days, HAC is advancing from “feature definition” to the “naming freeze + semantic wrap-up” stage, moving one step closer to formal review/ratification — fully aligned with this week’s official RISC-V security/cryptography thrust (Spectre paper, SPMP, riscv-security-model).

1.2 XiangShan Main Branch Merges 13 Commits in Batch: Pc Class Refactor, TLB/FTQ Fixes, BTB Replacement Policy Optimization

Date: 2026-08-18 10:41 (Beijing Time, batch merge)　Source: OpenXiangShan/XiangShan GitHub

The XiangShan main branch merged 13 commits in batch at 02:41 UTC (10:41 Beijing Time) on 08-18, most of which were backlog merges with author dates from 07-22 to 08-13, plus one new commit from the same day:

Same-day new commit: perf(btb): update btb replacer using training touch strategy instead of prediction touch strategy — the BTB replacer switches from a “prediction touch” strategy to a “training touch” strategy, an algorithm-level optimization of branch target buffer replacement;
Refactor thrust: refactor(pc): add Pc class to replace PrunedAddr(VAddrBits) + docs(Pc): add scaladoc + feat(PrunedAddr): add a strict mode — a refactor batch migrating frontend PC representation from PrunedAddr to the new Pc class;
TLB/CSR correctness fix batch (author dates 07-22 to 07-27): ITLB/DTLB overflow bit differentiation (bit[49]/bit[50]), gpaddr truncation width, non-canonical bit trap address preservation, instruction TLB pre-checks (pf/gpf/af), FTQ/Backend pcMem→CtrlBlock→CSR bit-width extension, etc.

XSAI (AI accelerator) concurrently merged fix(rob): assert AMU request lane ordering (author date 08-12). The XiangShan main branch has seen batch merges on two consecutive days, maintaining an active development cadence.

1.3 riscv-unified-db: Two Instruction Semantics Fixes — Vector CSR Bit Width, Compressed FP Load/Store Register File

Date: 2026-08-18 16:25–16:44 (Beijing Time)　Source: riscv/riscv-unified-db GitHub

The official RISC-V Unified Database (unified-db) merged two semantics-level fixes within the window:

fix(csr): seven vector CSRs take XLEN, not MXLEN (#2489) — seven vector CSRs (vstart/vxsat/vxrm/vcsr/vlenb/vtype, etc.) take XLEN rather than MXLEN;
fix(isa): compressed FP load/stores must use the float register file (#2491) — compressed floating-point load/store instructions must use the floating-point register file.

As the single machine-readable source of instruction semantics for toolchains such as arch-test and Sail, UDB’s low-level fixes of this kind directly affect test and simulation correctness, constituting “specification infrastructure”-level maintenance (the third consecutive day such dynamics have been covered).

1.4 riscv-isa-manual: Clarify That MXR Does Not Affect M-Mode Pointer Masking

Date: 2026-08-18 21:18 (Beijing Time)　Source: riscv/riscv-isa-manual GitHub

The official ISA manual merged Clarify that MXR doesn't affect M-mode pointer masking (#3318): the MXR (Make eXecutable Readable) bit does not apply to address translation under M-mode pointer masking (Smmpm) — a clarification of the interaction semantics between the pointer masking extension and privilege modes; there was also routine maintenance in Update marchid contact for Coreblocks (#3190). Pointer masking and the SPMP covered in 1.4 both belong to this week’s address-security thrust.

1.5 Open-Source Project Watch

HN: RISC-V Extension Landscape (published 08-18 09:11 Beijing Time, 2 points): rpsene (Renan Sena) released an interactive RISC-V extension landscape map (page), visually summarizing the RISC-V extension families for developers navigating the ecosystem. HN link
meta-riscv / riscv-glossary / learn, etc.: routine maintenance (dependency upgrades, link checks), no substantive new content.

II. Product and Ecosystem Updates

2.1 Headline: T-Head Officially Announces XuanTie C950 Natively Runs Qwen-3.8 27B — A “Day 0” Moment for RISC-V LLM Inference

Date: 2026-08-18 (Wccftech reported at 08-19 00:10 Beijing time)　Source: Wccftech

Alibaba’s T-Head (T-Head Xuantie RISC-V team) officially announced that its flagship RISC-V chip XuanTie C950 provides Day 0 (support at launch) native inference support for the latest open-source model Qwen-3.8 27B, with specific metrics: 64-core C950 (with RVV vector extension) achieves 30 tokens/s decode speed and only 1.9 seconds time-to-first-token (TTFT). Key points:

Chip background: C950 was released in March 2026, positioned as a “server-class RISC-V processor for edge AI” — a single chip with 64 compute cores, clocked up to 3.20 GHz, executing AI workloads without relying on a GPU; equipped with standard L1, flexible configurable L2, optional shared L3, and hardware-level intelligent data prefetching. Manufactured on TSMC 5nm (according to Wccftech).
Model background: Qwen-3.8 27B is a 27-billion-parameter open-weight model, officially claimed to match Opus 4.5 in coding capability, and can run on a single MacBook (32GB memory) — a “mid-size, high cost-performance” inference model.
Strategic significance: This is another move in Alibaba’s “NVIDIA-like vertical integration” playbook — Day 0 optimization of its self-developed chip for its self-developed model, forming a “model-chip-cloud” closed loop; C950 can be combined with its data center AI accelerators to offload inference workloads.

This is one of the most landmark advances for the RISC-V camp in 2026 in the direction of “on-device/edge LLM inference”: previous RISC-V LLM demonstrations mostly remained at small models or quantized distillation, whereas C950 running a 27B-class model on 64-core RVV achieves usable throughput, validating the feasibility of the RISC-V multi-core + vector extension route in inference scenarios (see 3.1 for an in-depth look at T-Head).

2.2 Xen Project Establishes Safety Committee (AMD/EPAM/Renesas as Founding Members), Advances Full RISC-V Release

Date: 2026-08-18 10:59 (Beijing time)　Source: The Register

The open-source Hypervisor Xen project has established a Safety Committee, with founding contributing members AMD, EPAM, Renesas, aiming to drive Xen toward compliance with formal functional safety standards such as IEC-61508 — targeting workload isolation scenarios in automotive, robotics, and similar domains (“partitioning robot brains”). It also established a new Premier Plus membership tier, serving organizations seeking functional safety certification. Boeing recently joined the Xen project, and according to The Register, its interest lies precisely in safety work. Connection to RISC-V: Xen’s update released earlier this month “advanced work toward a full functional release for RISC-V processors” — Xen on RISC-V is one step closer to full usability. Functional safety at the virtualization layer (isolation, partitioning, certification) is directly relevant to RISC-V’s deployment in automotive/robotics and warrants tracking.

III. Domestic Team Updates and Deep Dives

3.1 T-Head XUANTIE-RV: C950 + Qwen Day 0 Officially Announced, zero_stage_boot Merges C920V5 Support

Date: 2026-08-18 / 19　Source: XUANTIE-RV GitHub / zero_stage_boot

C950 Ecosystem: Beyond the Qwen-3.8 27B Day 0 support covered in 2.1, groundwork for C950 already exists in XUANTIE-RV’s open-source repos — zero_stage_boot merged feature: Update for C950 (#66) (zero-stage boot support for C950) back in May, and this week merged [TMP]feat: Add support for C920V5 (C920V5 support, authored 08-12, merged 08-18 17:11 Beijing time) plus related resource links in the README. T-Head’s “chip launch — boot code — model inference stack” full-chain cadence is clear: the C950 hardware/software ecosystem is moving from “launch” to “running models.”
Organization Activity: XUANTIE-RV has 72 public repos in total; within the window only zero_stage_boot saw pushes (opensbi remains stalled at 08-15). But combined with the news-side announcement, T-Head’s actual focus this week was on C950 model adaptation and launch cadence, with public repo activity centered on boot code iteration.
Background: The C950 launch timing (2026-03) aligns with the “T-Head open-sources opensbi/zero_stage_boot” approach — boot firmware open-sourced first, model stack advancing on the product cadence. This is the hardware foundation for Alibaba’s “NVIDIA-style vertical integration” narrative.

3.2 SpacemiT spacemit-com: Vision Model Zoo Adds DEIMv2 Detector, RL Runtime Fix Merged to Main

Date: 2026-08-18 (20:16 / 13:49 Beijing time)　Source: model-zoo-vision / model_zoo_rl

model-zoo-vision merged feat(deimv2): add DEIMv2 COCO object detector (#74) (08-18 20:16 Beijing time) — adds the DEIMv2 COCO object detector (DEIM is an efficient DETR-family real-time detection architecture, targeting low-latency object detection); same day merged refactor(vision): return error for unsupported intent (#75). Continues the K1/K3 vision model zoo expansion cadence (previously included YOLOP/YOLOPv2 road-scene models).
model_zoo_rl (K3 humanoid robot RL runtime) merged fix(rl): use imported Eigen CMake target (#8) (08-18 13:49 Beijing time) — the fix/eigen-cmake-target branch fix from yesterday’s report is now formally merged to main; the RL inference stack (including SPERT NPU full-image inference, robot-test CI, per-policy kp/kd) enters the “merged to main” stage.
Other: ai-sdk saw two submodule updates (vision, rl); mpp (multimedia framework) saw branch-level pushes.

3.3 Sophgo: sophon-tools Continues Batch Agent Merges (OTA Flash Lock, Chinese Tokenization RAG, SophUI Terminal)

Date: 2026-08-18　Source: sophgo/sophon-tools GitHub

sophon-tools saw 10+ merges via AI agent branches within the window (continuing yesterday’s pattern): fix(bmssm): OTA 刷机/回滚窗口全程持 hazard 互斥锁，刷机中 reboot/shutdown 返回 409 (MYS-451) (flash safety lock), fix(se-rag-core): 中文 2-gram 分词 + doctor 指纹比对 provider/model (MYS-393), fix(se-rag-core): chunker 行号偏移与 ChunkID 冲突修复 (MYS-392), fix(psophliteos): 审计 Bearer 前缀 + 移除硬编码 admin 口令 (MYS-382), fix(SophUI): 内嵌终端退出后窗口常驻自动重登, etc. These are AI-agent-driven refactors of Sophgo’s developer toolchain (internal infrastructure), with no business impact assessment.

3.4 Espressif / Nuclei / ESWIN: Routine or Silent

Espressif: 39 repos saw pushes, all routine syncs — llvm-project upstream sync (08-19 08:13 Beijing time), routine updates to esp-idf/arduino-esp32/openthread/esp-nimble/esp-mqtt, etc. No feature-level developments.
Nuclei Nuclei-Software: No new pushes in the window (most recent 08-11).
ESWIN eswincomputing: No new pushes (most recent 07-14); public repos remain silent.

3.5 Domestic Team Organization Activity Snapshot (GitHub API, within window)

IV. Focus Chapter: Embodied Intelligence and Robotics

4.1 Safety Virtualization Enters the Stage: Xen Security Committee Targets “Robotic Workload Isolation”

The Xen project has established a security committee (founding members AMD/EPAM/Renesas) and is pursuing IEC-61508 compliance, explicitly listing “robotics” as a target scenario for workload isolation — a “partitioned robot brain” means isolated execution of mixed-criticality workloads (real-time control, navigation, perception) on the same hardware becomes a certifiable path. Significance for RISC-V embodied intelligence: Xen’s RISC-V support is advancing toward a “full-feature release.” If a safety-certified virtualization layer for automotive/robotics lands on RISC-V, it would fill in a third isolation form beyond the “real-time core + application core” dual-core heterogeneous approach (Dishui Lake Forum roadmap) — namely, VM-level partitioning. The combination of Renesas (a major automotive MCU player) + AMD also hints at the committee’s multi-architecture positioning.

4.2 C950 Running a 27B Model: Embodied Intelligence Potential of RISC-V Edge Large-Model Inference

C950 (64-core RVV, 3.2 GHz, 30 tok/s) validates the viability of the RISC-V multi-core + vector approach for 27B-class model inference. For embodied intelligence, on-device/edge large-model inference is a key link in “moving the brain upward” — if VLA (vision-language-action) models can achieve usable throughput on RISC-V platforms, it would reduce the whole system’s dependence on GPUs. Although C950 is currently positioned as an edge server rather than embedded (power/volume still far from robot-body deployment), it is a landmark step in “RISC-V running large models” from demo to product, providing baseline data for future mid-size chip downscaling (30 tok/s / 1.9s TTFT can serve as a reference frame for similar solutions).

4.3 SpacemiT “Perception-Decision-Motion Control” Stack Update

model-zoo-vision adds the DEIMv2 COCO detector (real-time detection direction), and model_zoo_rl’s Eigen build fix merges to main — SpacemiT’s K3 humanoid RL runtime and vision model zoo continue dual-track advancement this week, consistent with its three-layer layout of “perception (vision) — decision (RL) — motion control (SPERT NPU).” The cadence is “maintenance + incremental,” with no major new releases.

V. Summary and Trend Observations

The only major news-side item: T-Head C950 natively running Qwen-3.8 27B (64-core RVV, 30 tok/s, TTFT 1.9s, Day 0 support) — one of the most practical advances for RISC-V in large-model inference, landing the “chip-model” vertical integration narrative; the same day zero_stage_boot merged C920V5 support, making T-Head’s focus this week clear.
HAC specification enters naming freeze after four days of intensive revisions (30+ items): Zl→Zkl renaming proposal, WARL rules, Smacestatus consolidation — one step closer to formal review, with RISC-V’s official security/crypto mainline continuing to strengthen.
Security and virtualization intersection heating up: Xen establishes a security committee (AMD/EPAM/Renesas, IEC-61508, robot partitioning) + riscv-isa-manual pointer masking clarification + riscv-security-model update — “functional safety certification” is becoming the next competitive focus for the RISC-V ecosystem (automotive/robotics/virtualization).
XiangShan main branch sees batch merges for a second consecutive day (13 items: Pc class refactor, TLB fix, BTB training touch replacement policy), maintaining an active development cadence; unified-db semantic fixes appear for a third consecutive day, with “specification infrastructure” maintenance intensity undiminished.
Domestic teams clearly diverging: T-Head (C950 ecosystem announcement + boot code), SpacemiT (DEIMv2/RL fix merged), Sophgo (agent-driven toolchain iteration) advancing on three fronts; Espressif routine, Nuclei/ESWIN silent.

Limitations: C950 announcement details (chip specs, process, metrics) are based on Wccftech’s relay, which itself cites an X platform post, and have not been directly verified against Alibaba’s official pages (the Wccftech original is accessible); Qwen-3.8 model本体 parameters (“benchmarked against Opus 4.5,” “runnable on a single MacBook”) are media claims; Xen’s RISC-V “full release” timeline has not been announced; sophon-tools merge contents are internal toolchain iterations with no business impact assessment performed.

Appendix: Complete Source List

No.	Event	Source Link
1	XuanTie C950 natively runs Qwen-3.8 27B (Wccftech)	Link
2	Xen Project establishes Safety Committee (The Register)	Link
3	HAC specification sees intensive revisions on day four (30+ commits)	Link
4	XiangShan main branch merges 13 commits in batch	Link
5	XSAI AMU assertion fix	Link
6	riscv-unified-db: two semantic fixes (#2489/#2491)	Link
7	riscv-isa-manual: pointer masking clarification (#3318)	Link
8	T-Head zero_stage_boot C920V5 support	Link
9	SpacemiT model-zoo-vision DEIMv2 (#74)	Link
10	SpacemiT model_zoo_rl Eigen fix merged (#8)	Link
11	Sophgo sophon-tools agent merged in batch	Link
12	RISC-V Extension Landscape (HN)	Link

Source Verification Table (Appendix for a Weak News Day)

| Source | Verification Result | |—|—| | Google News “RISC-V when:2d” (bare query to verify proxy) | Valid (9 items): XuanTie C950 (included), Xen Safety Committee (included); VIHAAN/ESP32-P4X-EYE/India C2S are follow-ups to items already reported on 08-17/18; Phoronix PowerPC Rust, GPU Rust, VirtualBox FRED (x86 feature) filtered out as noise; China open-source roundups with no RISC-V details filtered out | | Vendor English queries (SiFive / Milk-V / SpacemiT / SOPHGO / StarFive / Andes when:3-7d) | SiFive/Milk-V/SpacemiT/SOPHGO: no hits; StarFive: only old 08-13 BMC news; Andes: hits on noise such as Chile’s AES Andes energy storage/universities; RISC-V Summit: only mentioned in Linux Foundation monthly report | | Chinese team keywords (T-Head/XiangShan/ESWIN/Nuclei/Espressif when:7d) | T-Head: hits on old Spectre news (already reported 08-12) + C950 (included); XiangShan: hits on Michelin Guide/stock buyback noise; ESWIN/Nuclei: no hits; Espressif: follow-ups to old ESP32-P4X-EYE news + Hackster DIY project | | gnews “XuanTie C950” when:7d | Exactly 1 hit (Wccftech, included) + 1 irrelevant AI noise item | | Direct RSS pulls (linuxgizmos / riscv.org / CNX / Phoronix) | No new RISC-V-specific items within the window: Phoronix only PowerPC Rust / GPU Rust noise, CNX no hits | | HN Algolia “riscv” (24h) | 1 item: RISC-V Extension Landscape (included) | | GitHub topic:risc-v pushed | Noise such as grain OS fork with 2 stars; personal profile noise | | Domestic org activity (GitHub API) | XUANTIE-RV/OpenXiangShan/spacemit-com/sophgo active (see main text for details); espressif routine; Nuclei/eswincomputing silent |